A List of Free and Open Source Hardware Verification Tools and Frameworks
☆597Jan 3, 2026Updated 2 months ago
Alternatives and similar repositories for awesome-open-hardware-verification
Users that are interested in awesome-open-hardware-verification are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Description Languages☆1,131Mar 17, 2026Updated last week
- A curated list of awesome resources for HDL design and verification☆170Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆369Updated this week
- The UVM written in Python☆514Mar 17, 2026Updated last week
- Code generation tool for control and status registers☆450Mar 14, 2026Updated 2 weeks ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- cocotb: Python-based chip (RTL) verification☆2,289Mar 19, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,398Feb 13, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆654Jan 19, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆454Mar 8, 2026Updated 3 weeks ago
- lowRISC Style Guides☆487Nov 6, 2025Updated 4 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,797Mar 13, 2026Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,528Mar 18, 2026Updated last week
- SystemVerilog to Verilog conversion☆710Nov 24, 2025Updated 4 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- List of awesome open source hardware tools, generators, and reusable designs☆2,290Mar 2, 2026Updated 3 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆142Mar 16, 2026Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Jan 31, 2022Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,265Mar 5, 2026Updated 3 weeks ago
- SystemVerilog compiler and language services☆989Mar 22, 2026Updated last week
- RISC-V Formal Verification Framework☆626Apr 6, 2022Updated 3 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆666Mar 8, 2026Updated 3 weeks ago
- An abstraction library for interfacing EDA tools☆756Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,468Updated this week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 4 months ago
- A curated list of awesome HDL, libraries, typical implementation and references.☆37Oct 19, 2016Updated 9 years ago
- Awesome ASIC design verification☆344Feb 9, 2022Updated 4 years ago
- Common SystemVerilog components☆728Updated this week
- ☆213Mar 22, 2026Updated last week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆779Jun 15, 2024Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆468Nov 4, 2025Updated 4 months ago
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languag…☆474Jan 18, 2026Updated 2 months ago
- SERV - The SErial RISC-V CPU☆1,773Feb 19, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,727Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,814Feb 17, 2026Updated last month
- SystemVerilog synthesis tool☆229Mar 10, 2025Updated last year
- Verilog library for ASIC and FPGA designers☆1,400May 8, 2024Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆500Updated this week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆286Nov 25, 2019Updated 6 years ago
- Build your hardware, easily!☆3,787Mar 21, 2026Updated last week