Alternatives and similar repositories for awesome-open-hardware-verification:

Users that are interested in awesome-open-hardware-verification are comparing it to the libraries listed below

• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆618Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆608Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆551Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆682Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆485Updated 2 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆423Updated 7 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,018Updated 2 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆420Updated last month
• pyuvm / pyuvm
  The UVM written in Python
  ☆422Updated 3 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆278Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆388Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆528Updated 3 weeks ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆427Updated 7 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆381Updated 2 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆490Updated 5 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,262Updated 2 weeks ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆688Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆315Updated 4 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆599Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆324Updated 10 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,276Updated 2 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆255Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆443Updated 3 years ago
• mattvenn / awesome-opensource-asic-resources
  ☆321Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆250Updated 2 weeks ago