hdl / awesome
A curated list of awesome resources for HDL design and verification
☆139Updated last week
Related projects ⓘ
Alternatives and complementary repositories for awesome
- FuseSoC standard core library☆112Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆109Updated last year
- Control and status register code generator toolchain☆99Updated 2 months ago
- ☆76Updated 8 months ago
- SystemVerilog synthesis tool☆168Updated this week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆51Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆198Updated last month
- Fabric generator and CAD tools☆148Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 4 months ago
- Generic Register Interface (contains various adapters)☆99Updated last month
- WAL enables programmable waveform analysis.☆136Updated 2 weeks ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆202Updated 2 weeks ago
- FPGA tool performance profiling☆101Updated 8 months ago
- Control and Status Register map generator for HDL projects☆99Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 5 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆132Updated last year
- OSVVM Documentation☆30Updated 3 weeks ago
- Framework Open EDA Gui☆60Updated this week
- SpinalHDL Hardware Math Library☆77Updated 3 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- SoC based on VexRiscv and ICE40 UP5K☆151Updated 7 months ago
- RISC-V Verification Interface☆74Updated 2 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆273Updated this week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆105Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated this week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆193Updated 2 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆140Updated last year
- Opensource DDR3 Controller☆203Updated last week
- A complete open-source design-for-testing (DFT) Solution☆135Updated last week
- HDL symbol generator☆185Updated last year