hdl / awesomeLinks
A curated list of awesome resources for HDL design and verification
☆169Updated this week
Alternatives and similar repositories for awesome
Users that are interested in awesome are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆153Updated 2 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆220Updated last month
- Streaming based VHDL parser.☆84Updated last year
- Building and deploying container images for open source electronic design automation (EDA)☆120Updated last year
- Playing around with Formal Verification of Verilog and VHDL☆65Updated 4 years ago
- OSVVM Documentation☆36Updated last month
- ☆91Updated 3 months ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆76Updated this week
- Example designs showing different ways to use F4PGA toolchains.☆283Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated last year
- HDL symbol generator☆201Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆82Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Updated 2 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆301Updated last week
- FPGA tool performance profiling☆105Updated last year
- Control and Status Register map generator for HDL projects☆130Updated 8 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆246Updated 5 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 3 months ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆83Updated 6 years ago
- A curated list of awesome HDL, libraries, typical implementation and references.☆37Updated 9 years ago
- SystemVerilog synthesis tool☆227Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- WAL enables programmable waveform analysis.☆164Updated 3 months ago
- Fabric generator and CAD tools.☆217Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- SystemVerilog frontend for Yosys☆196Updated this week