Alternatives and similar repositories for awesome:

Users that are interested in awesome are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆138Updated 2 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆145Updated 10 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆211Updated 5 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆163Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• pieter3d / simview
  ☆78Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆283Updated this week
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆56Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆98Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆117Updated 7 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆179Updated 3 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated last month
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆60Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆89Updated 2 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 3 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆275Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆178Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆190Updated 2 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆149Updated 2 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated this week
• olofk / corescore
  CoreScore
  ☆151Updated 3 months ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆63Updated 11 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago