hdl / awesomeLinks
A curated list of awesome resources for HDL design and verification
☆156Updated this week
Alternatives and similar repositories for awesome
Users that are interested in awesome are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆146Updated 2 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆215Updated 3 weeks ago
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated 10 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆140Updated 2 years ago
- Streaming based VHDL parser.☆84Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- OSVVM Documentation☆35Updated 2 weeks ago
- Fabric generator and CAD tools.☆192Updated last week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆292Updated this week
- Control and Status Register map generator for HDL projects☆121Updated 2 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆154Updated last month
- FPGA tool performance profiling☆102Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆224Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- An open-source HDL register code generator fast enough to run in real time.☆72Updated last month
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 6 months ago
- HDL symbol generator☆193Updated 2 years ago
- SystemVerilog frontend for Yosys☆148Updated last week
- ☆337Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- ☆79Updated last year
- Control and status register code generator toolchain☆142Updated 2 months ago
- SystemVerilog synthesis tool☆206Updated 4 months ago
- FPGA and Digital ASIC Build System☆76Updated 3 weeks ago
- A curated list of awesome HDL, libraries, typical implementation and references.☆38Updated 8 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆184Updated 2 weeks ago
- Open-source FPGA research and prototyping framework.☆208Updated 11 months ago