Alternatives and similar repositories for symbolator:

Users that are interested in symbolator are comparing it to the libraries listed below

• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆159Updated this week
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆183Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 2 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆132Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆122Updated last month
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆115Updated this week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆209Updated 4 months ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆237Updated last week
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 5 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆58Updated last week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆157Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated 2 weeks ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆204Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆111Updated last year
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆205Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆250Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆120Updated last month
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆382Updated this week
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 3 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆82Updated 8 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 9 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated 2 weeks ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆161Updated last year
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆102Updated last year
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆68Updated 3 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆251Updated last year
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆387Updated 2 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆63Updated 6 months ago