HDL symbol generator
☆206Feb 2, 2023Updated 3 years ago
Alternatives and similar repositories for symbolator
Users that are interested in symbolator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Simple parser for extracting VHDL documentation☆75Jul 12, 2024Updated 2 years ago
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- Flexible VHDL library☆200Jun 28, 2023Updated 3 years ago
- A JSON library implemented in VHDL.☆87Jul 13, 2026Updated 3 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆335Jun 30, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- An abstract language model of VHDL written in Python.☆66Updated this week
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Style guide enforcement for VHDL☆256Sep 6, 2026Updated last month
- VUnit is a unit testing framework for VHDL/SystemVerilog☆854Updated this week
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 3 years ago
- draws an SVG schematic from a JSON netlist☆839Jan 25, 2024Updated 2 years ago
- bit field diagram renderer☆396Oct 25, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 11 months ago
- Repurposing existing HDL tools to help writing better code☆228Sep 23, 2026Updated last month
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆267Oct 24, 2026Updated last week
- Streaming based VHDL parser.☆86Oct 26, 2026Updated last week
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Oct 20, 2019Updated 7 years ago
- VHDL-2008 Support Library☆62Oct 11, 2016Updated 10 years ago
- Language server based on ghdl☆104Aug 1, 2026Updated 3 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆467Updated this week
- A Sphinx domain providing VHDL language support.☆21Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Virtual development board for HDL design☆44Mar 31, 2023Updated 3 years ago
- An abstraction library for interfacing EDA tools☆803Sep 15, 2026Updated last month
- VHDLproc is a VHDL preprocessor☆25May 12, 2022Updated 4 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆607Jul 30, 2025Updated last year
- VHDL compiler and simulator☆904Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆745Oct 11, 2026Updated 3 weeks ago
- A fast VHDL language server and analysis library written in Rust☆516Updated this week
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 10 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,482Oct 23, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆227Oct 16, 2026Updated 2 weeks ago
- Hardware Description Languages☆1,183Oct 27, 2026Updated last week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆56Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆476Updated this week
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 6 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- ☆28Mar 17, 2026Updated 7 months ago