HDL symbol generator
☆202Feb 2, 2023Updated 3 years ago
Alternatives and similar repositories for symbolator
Users that are interested in symbolator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Simple parser for extracting VHDL documentation☆73Jul 12, 2024Updated last year
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- Flexible VHDL library☆196Jun 28, 2023Updated 2 years ago
- A JSON library implemented in VHDL.☆84Feb 8, 2026Updated 3 months ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An abstract language model of VHDL written in Python.☆64May 11, 2026Updated 2 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆325Jun 30, 2025Updated 10 months ago
- A Sphinx domain providing VHDL language support.☆21Dec 18, 2023Updated 2 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆825May 14, 2026Updated last week
- bit field diagram renderer☆392Feb 22, 2024Updated 2 years ago
- draws an SVG schematic from a JSON netlist☆794Jan 25, 2024Updated 2 years ago
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆258May 15, 2026Updated last week
- Language server based on ghdl☆103May 16, 2026Updated last week
- Style guide enforcement for VHDL☆240Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- VHDL-2008 Support Library☆62Oct 11, 2016Updated 9 years ago
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated 2 weeks ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 6 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆37Dec 24, 2020Updated 5 years ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Oct 20, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆605Jul 30, 2025Updated 9 months ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 months ago
- Hardware Description Languages☆1,148Apr 6, 2026Updated last month
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆52Updated this week
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆715Dec 14, 2025Updated 5 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆429Apr 22, 2026Updated last month
- This repository contains synthesizable examples which use the PoC-Library.☆39Dec 24, 2020Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 3 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 19, 2026Updated last week
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- Code generation tool for control and status registers☆455Apr 19, 2026Updated last month