Alternatives and similar repositories for vunit:

Users that are interested in vunit are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆394Updated 3 weeks ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆577Updated 4 years ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,265Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆237Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,948Updated this week
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆382Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆675Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆441Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆537Updated 2 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆649Updated 5 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆606Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆613Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆421Updated 3 weeks ago
• nickg / nvc
  VHDL compiler and simulator
  ☆683Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆599Updated 3 weeks ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆275Updated 5 years ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆204Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆387Updated 2 weeks ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆795Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆312Updated this week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆333Updated this week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆572Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,040Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆565Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆700Updated 10 months ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆718Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆381Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆415Updated 7 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆433Updated last month
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,074Updated this week