PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
☆747Sep 3, 2026Updated this week
Alternatives and similar repositories for PipelineC
Users that are interested in PipelineC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design digital circuits in C. Simulate really fast with a regular compiler.☆183Jan 16, 2026Updated 7 months ago
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,431Aug 23, 2026Updated last week
- Graphics demos☆111Mar 22, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆793Aug 12, 2026Updated 3 weeks ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆789Jan 28, 2026Updated 7 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework☆97Aug 25, 2026Updated last week
- Universal utility for programming FPGA☆1,721Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆680Jul 7, 2026Updated last month
- Build your hardware, easily!☆4,071Updated this week
- SERV - The SErial RISC-V CPU☆1,880Aug 25, 2026Updated last week
- A modern hardware definition language and toolchain based on Python☆2,078Updated this week
- Hardware Description Languages☆1,170Jul 9, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆474Updated this week
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,668Nov 18, 2025Updated 9 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Aug 25, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,453Aug 24, 2026Updated last week
- XLS: Accelerated HW Synthesis☆1,869Updated this week
- A Python toolbox for building complex digital hardware☆1,329Jan 5, 2026Updated 8 months ago
- SystemVerilog to Verilog conversion☆750Aug 18, 2026Updated 2 weeks ago
- nextpnr portable FPGA place and route tool☆1,745Updated this week
- An Open-source FPGA IP Generator☆1,142Updated this week
- cocotb: Python-based chip (RTL) verification☆2,489Updated this week
- Yosys Open SYnthesis Suite☆4,735Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,254Updated this week
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆151Aug 26, 2026Updated last week
- Scala based HDL☆2,033Updated this week
- Send video/audio over HDMI on an FPGA☆1,291Jul 13, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆829Jul 13, 2026Updated last month
- PandA-bambu public repository☆351Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,240Updated this week
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆472Sep 13, 2024Updated last year
- Documenting the Xilinx 7-series bit-stream format.☆908Jun 5, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Communication framework for RTL simulation and emulation.☆320Updated this week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆261Jul 31, 2026Updated last month
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆466Jul 2, 2026Updated 2 months ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- A small, light weight, RISC CPU soft core☆1,579Aug 19, 2026Updated 2 weeks ago
- HDL symbol generator☆205Feb 2, 2023Updated 3 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,928Updated this week