A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
☆702Feb 23, 2026Updated last week
Alternatives and similar repositories for PipelineC
Users that are interested in PipelineC are comparing it to the libraries listed below
Sorting:
- Design digital circuits in C. Simulate really fast with a regular compiler.☆178Jan 16, 2026Updated last month
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,398Jan 5, 2026Updated 2 months ago
- Graphics demos☆111Mar 22, 2024Updated last year
- Universal utility for programming FPGA☆1,554Feb 26, 2026Updated last week
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆752Jan 28, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,761Feb 19, 2026Updated 2 weeks ago
- Build your hardware, easily!☆3,747Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- A modern hardware definition language and toolchain based on Python☆1,914Updated this week
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆94Feb 17, 2026Updated 2 weeks ago
- Hardware Description Languages☆1,116Jul 14, 2025Updated 7 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,391Feb 13, 2026Updated 3 weeks ago
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,416Nov 18, 2025Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆450Updated this week
- A Python toolbox for building complex digital hardware☆1,322Jan 5, 2026Updated 2 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Dec 23, 2025Updated 2 months ago
- SystemVerilog to Verilog conversion☆706Nov 24, 2025Updated 3 months ago
- XLS: Accelerated HW Synthesis☆1,428Updated this week
- Yosys Open SYnthesis Suite☆4,305Updated this week
- cocotb: Python-based chip (RTL) verification☆2,266Updated this week
- An Open-source FPGA IP Generator☆1,056Feb 28, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- nextpnr portable FPGA place and route tool☆1,627Updated this week
- Scala based HDL☆1,929Updated this week
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated 3 weeks ago
- Send video/audio over HDMI on an FPGA☆1,254Feb 3, 2024Updated 2 years ago
- Documenting the Xilinx 7-series bit-stream format.☆851Jun 5, 2025Updated 9 months ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,993Updated this week
- PandA-bambu public repository☆315Feb 10, 2026Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆446Aug 24, 2025Updated 6 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆463Sep 13, 2024Updated last year
- Small footprint and configurable DRAM core☆475Feb 19, 2026Updated 2 weeks ago
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 2 months ago
- Modular hardware build system☆1,131Updated this week
- SystemVerilog compiler and language services☆968Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,498Jan 7, 2026Updated last month