SystemVerilog linter
☆377Nov 6, 2025Updated 3 months ago
Alternatives and similar repositories for svlint
Users that are interested in svlint are comparing it to the libraries listed below
Sorting:
- SystemVerilog language server☆560Feb 20, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 3 months ago
- A SystemVerilog Language Server☆194Nov 30, 2025Updated 3 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,776Dec 22, 2025Updated 2 months ago
- SystemVerilog compiler and language services☆961Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆449Feb 23, 2026Updated last week
- ☆130Nov 17, 2025Updated 3 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆360Updated this week
- SystemVerilog to Verilog conversion☆704Nov 24, 2025Updated 3 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Veryl: A Modern Hardware Description Language☆893Updated this week
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- Open source implementation of a Verilog formatter☆181Jan 27, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆755Feb 18, 2026Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆3,381Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆491Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆250Feb 22, 2026Updated last week
- Common SystemVerilog components☆713Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- A dependency management tool for hardware projects.☆347Updated this week
- The UVM written in Python☆502Updated this week
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- Code generation tool for control and status registers☆448Jan 7, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,500Updated this week
- cocotb: Python-based chip (RTL) verification☆2,255Feb 21, 2026Updated last week
- SystemVerilog support in VS Code☆149Feb 18, 2025Updated last year
- A fast VHDL language server and analysis library written in Rust☆462Feb 22, 2026Updated last week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆914Feb 23, 2026Updated last week
- Hardware Description Languages☆1,115Jul 14, 2025Updated 7 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆317Jun 30, 2025Updated 8 months ago
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆694Dec 14, 2025Updated 2 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,389Feb 13, 2026Updated 2 weeks ago
- Python bindings for slang, a library for compiling SystemVerilog☆66Jan 18, 2025Updated last year
- A SystemVerilog source file pickler.☆60Oct 20, 2024Updated last year
- RISC-V Formal Verification Framework☆625Apr 6, 2022Updated 3 years ago
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- Yosys Open SYnthesis Suite☆4,293Updated this week