Alternatives and similar repositories for svlint

Users that are interested in svlint are comparing it to the libraries listed below

• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆444Updated 4 months ago
• dalance / svls
  SystemVerilog language server
  ☆517Updated this week
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆175Updated 3 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆333Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆399Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆311Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆406Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆648Updated 3 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 3 weeks ago
• imc-trading / svlangserver
  ☆115Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆634Updated last week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆255Updated last week
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆214Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆587Updated this week
• VHDL-LS / rust_hdl
  ☆413Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆510Updated 5 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 4 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆440Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆394Updated 6 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆179Updated 7 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆461Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 3 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆328Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆790Updated this week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆625Updated 3 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆288Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆292Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆260Updated 2 months ago