draws an SVG schematic from a JSON netlist
☆829Jan 25, 2024Updated 2 years ago
Alternatives and similar repositories for netlistsvg
Users that are interested in netlistsvg are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- D3.js and ELK based schematic visualizer☆123May 13, 2026Updated 4 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 3 years ago
- Yosys Open SYnthesis Suite☆4,803Updated this week
- HDL symbol generator☆206Feb 2, 2023Updated 3 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆334Jun 30, 2025Updated last year
- nextpnr portable FPGA place and route tool☆1,771Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- SystemVerilog compiler and language services☆1,161Updated this week
- cocotb: Python-based chip (RTL) verification☆2,539Updated this week
- D3.js based wave (signal) visualizer☆68Jun 9, 2026Updated 4 months ago
- SystemVerilog to Verilog conversion☆755Aug 18, 2026Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,958Sep 23, 2026Updated 2 weeks ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated 3 weeks ago
- Hardware Description Languages☆1,181Jul 9, 2026Updated 3 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,475Sep 25, 2026Updated 2 weeks ago
- Building and deploying container images for open source electronic design automation (EDA)☆123Oct 1, 2026Updated last week
- VHDL compiler and simulator☆890Updated this week
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 5 years ago
- VHDL synthesis (based on ghdl)☆370Sep 20, 2026Updated 3 weeks ago
- A modern hardware definition language and toolchain based on Python☆2,104Sep 18, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A mixed signal netlist language (pre-alpha)☆62Aug 20, 2018Updated 8 years ago
- magma circuits☆264Oct 19, 2024Updated last year
- Universal utility for programming FPGA☆1,753Oct 6, 2026Updated last week
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆499Updated this week
- A Parser for KiCad EESCHEMA netlists.☆27Jan 22, 2026Updated 8 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆1,031Updated this week
- An open-source static random access memory (SRAM) compiler.☆1,153Oct 2, 2026Updated last week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆49Feb 12, 2026Updated 8 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,273Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆242Updated this week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,966Mar 25, 2026Updated 6 months ago
- Digital timing diagram rendering engine☆3,507Aug 31, 2026Updated last month
- Build your hardware, easily!☆4,155Updated this week
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 4 months ago
- A High-performance Timing Analysis Tool for VLSI Systems☆720Dec 26, 2025Updated 9 months ago