nturley / netlistsvg

Related projects ⓘ

Alternatives and complementary repositories for netlistsvg

• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,314Updated last month
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆495Updated this week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆570Updated 2 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆564Updated 3 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆361Updated last month
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆645Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,206Updated 2 weeks ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆381Updated last year
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆774Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆742Updated this week
• nickg / nvc
  VHDL compiler and simulator
  ☆636Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,017Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,305Updated last month
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆308Updated 4 months ago
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,230Updated last month
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,218Updated last week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,002Updated 3 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆408Updated 2 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆368Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,442Updated last week
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆290Updated 3 years ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆267Updated 7 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆407Updated 2 weeks ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆402Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆347Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆273Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆587Updated last month
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆387Updated last year
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆858Updated this week