draws an SVG schematic from a JSON netlist
☆809Jan 25, 2024Updated 2 years ago
Alternatives and similar repositories for netlistsvg
Users that are interested in netlistsvg are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- D3.js and ELK based schematic visualizer☆122May 13, 2026Updated 2 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- Yosys Open SYnthesis Suite☆4,622Updated this week
- HDL symbol generator☆204Feb 2, 2023Updated 3 years ago
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆330Jun 30, 2025Updated last year
- nextpnr portable FPGA place and route tool☆1,712Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆467Updated this week
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- SystemVerilog compiler and language services☆1,090Updated this week
- cocotb: Python-based chip (RTL) verification☆2,450Updated this week
- D3.js based wave (signal) visualizer☆68Jun 9, 2026Updated last month
- SystemVerilog to Verilog conversion☆741Mar 28, 2026Updated 3 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,895Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated 3 weeks ago
- Hardware Description Languages☆1,162Jul 9, 2026Updated 2 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,439Jul 2, 2026Updated 3 weeks ago
- VHDL compiler and simulator☆863Updated this week
- Web-based HDL diagramming tool☆85May 1, 2023Updated 3 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- VHDL synthesis (based on ghdl)☆369Jun 22, 2026Updated last month
- A modern hardware definition language and toolchain based on Python☆2,056Jul 16, 2026Updated last week
- A mixed signal netlist language (pre-alpha)☆61Aug 20, 2018Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Universal utility for programming FPGA☆1,689Jul 14, 2026Updated last week
- magma circuits☆264Oct 19, 2024Updated last year
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆482Jul 15, 2026Updated last week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 5 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆993Jun 18, 2026Updated last month
- A Parser for KiCad EESCHEMA netlists.☆27Jan 22, 2026Updated 6 months ago
- An open-source static random access memory (SRAM) compiler.☆1,095Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆239Updated this week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,868Mar 25, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Digital timing diagram rendering engine☆3,446Jul 8, 2026Updated 2 weeks ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,253Updated this week
- Build your hardware, easily!☆4,007Updated this week
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- A High-performance Timing Analysis Tool for VLSI Systems☆707Dec 26, 2025Updated 6 months ago
- A complete open-source design-for-testing (DFT) Solution☆199Aug 30, 2025Updated 10 months ago