Veryl: A Modern Hardware Description Language
☆941May 22, 2026Updated last week
Alternatives and similar repositories for veryl
Users that are interested in veryl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog linter☆383Nov 6, 2025Updated 6 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆472Mar 30, 2026Updated 2 months ago
- Code generation tool for control and status registers☆459Updated this week
- Let's write RISC-V CPU in Veryl!☆63Feb 12, 2026Updated 3 months ago
- SystemVerilog language server☆572Apr 2, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Basic Common Modules☆48Apr 30, 2026Updated last month
- Filelist generator☆21Apr 23, 2026Updated last month
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆106May 3, 2026Updated 3 weeks ago
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated 10 months ago
- A framework for writing FPGA firmware using the Rust Programming Language☆486Jun 3, 2025Updated 11 months ago
- RISC-V instruction decoder written in Rust.☆17Dec 31, 2025Updated 4 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,849Mar 13, 2026Updated 2 months ago
- A dependency management tool for hardware projects.☆370May 22, 2026Updated last week
- SystemVerilog compiler and language services☆1,049Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Verilator open-source SystemVerilog simulator and lint system☆3,637Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- Fearless hardware design☆203Aug 20, 2025Updated 9 months ago
- Hardware Description Languages☆1,148Apr 6, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463Updated this week
- Yosys Open SYnthesis Suite☆4,464May 23, 2026Updated last week
- LL(k) and LALR(1) parser generator for Rust and C#☆235May 22, 2026Updated last week
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆149Mar 29, 2026Updated 2 months ago
- SystemVerilog synthesis tool☆233Mar 10, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,414May 20, 2026Updated last week
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated 10 months ago
- A SystemVerilog Language Server☆199Nov 30, 2025Updated 5 months ago
- Intermediate Language (IL) for Hardware Accelerator Generators☆596May 10, 2026Updated 2 weeks ago
- XLS: Accelerated HW Synthesis☆1,493Updated this week
- Universal utility for programming FPGA☆1,635May 19, 2026Updated last week
- Circuit IR Compilers and Tools☆2,141Updated this week
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Mar 3, 2025Updated last year
- An HDL embedded in Rust.☆204Nov 15, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A fast VHDL language server and analysis library written in Rust☆486Updated this week
- cocotb: Python-based chip (RTL) verification☆2,379May 22, 2026Updated last week
- Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html☆11Feb 5, 2019Updated 7 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,416May 10, 2026Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆730Mar 28, 2026Updated 2 months ago
- WAL enables programmable waveform analysis.☆179Nov 10, 2025Updated 6 months ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month