Alternatives and similar repositories for svinst:

Users that are interested in svinst are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆55Updated 4 months ago
• antmicro / verilator-verification-features-tests
  ☆18Updated this week
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆76Updated this week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆52Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆44Updated 4 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆44Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated last month
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 7 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 7 months ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 11 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆44Updated 7 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆56Updated 2 months ago
• chipsalliance / uvm-verilator
  ☆87Updated last year
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆28Updated 9 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆62Updated 4 months ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆33Updated 4 months ago
• chipsalliance / fpga-interchange-schema
  ☆54Updated 2 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated last month
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago