Alternatives and similar repositories for uvm-python

Users that are interested in uvm-python are comparing it to the libraries listed below

• svunit / svunit
  ☆208Updated 8 months ago
• raysalemi / Python4RTLVerification
  ☆168Updated 3 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆296Updated last month
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆202Updated 8 years ago
• accellera-official / uvm-core
  ☆98Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆479Updated last week
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated last year
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last month
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆85Updated 4 years ago
• accellera / uvm
  ☆57Updated 9 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆163Updated last month
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆263Updated last week
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆150Updated 7 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆106Updated 2 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆129Updated last month
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆156Updated 5 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆426Updated last year
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆207Updated 5 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆144Updated 4 years ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆109Updated 11 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆283Updated 3 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆75Updated 5 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆263Updated 12 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆88Updated 8 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆148Updated 4 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated last month
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆224Updated 2 years ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆145Updated 8 months ago