Filelist generator
☆21Jun 9, 2026Updated this week
Alternatives and similar repositories for flgen
Users that are interested in flgen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆33Nov 25, 2022Updated 3 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- SystemVerilog file list pruner☆19Mar 2, 2026Updated 3 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 10 months ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)☆23Dec 5, 2024Updated last year
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 4 months ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 8 years ago
- A SystemVerilog source file pickler.☆61Oct 20, 2024Updated last year
- The Diderot language compiler☆15Mar 13, 2023Updated 3 years ago
- Basic Common Modules☆48Jun 5, 2026Updated last week
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- ☆37Sep 19, 2024Updated last year
- Yosys plugin for logic locking and supply-chain security☆24Apr 5, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆39Nov 6, 2025Updated 7 months ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆16Mar 3, 2026Updated 3 months ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Veryl: A Modern Hardware Description Language☆952Jun 8, 2026Updated last week
- Open-source IPs Package Manager (IPM)☆16Feb 24, 2025Updated last year
- Mutation Cover with Yosys (MCY)☆92Jun 2, 2026Updated last week
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated 2 months ago
- ☆25Apr 12, 2026Updated 2 months ago
- Code generation tool for control and status registers☆463May 30, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- EDA Analytics Central☆16Dec 8, 2022Updated 3 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- VHDL code generator for AXI4-lite register files☆12May 22, 2024Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆33Oct 15, 2024Updated last year
- Files and documentation for Pico-Dirty-Blaster Workshop☆20Jun 21, 2025Updated 11 months ago
- ☆10Apr 8, 2021Updated 5 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 4 months ago
- ☆38Aug 31, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Debug waveforms with GDB☆33Nov 12, 2025Updated 7 months ago
- Open Processor Architecture☆26Apr 7, 2016Updated 10 years ago
- RISC-V by VectorBlox☆18Dec 14, 2015Updated 10 years ago
- An infrastructure for integrated EDA☆42Jul 20, 2023Updated 2 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆18Nov 11, 2025Updated 7 months ago
- Making cocotb testbenches that bit easier☆39Feb 28, 2026Updated 3 months ago
- ☆45Jun 3, 2026Updated last week