Alternatives and similar repositories for flgen:

Users that are interested in flgen are comparing it to the libraries listed below

• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 months ago
• pulp-platform / svase
  ☆31Updated 3 months ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆37Updated 4 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated last month
• taichi-ishitani / tue
  Useful UVM extensions
  ☆22Updated 9 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated 2 weeks ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 5 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆68Updated 8 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• pulp-platform / ELAU
  ☆13Updated 9 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆26Updated 10 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last week
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆56Updated 3 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated 2 months ago
• rggen / rggen-systemverilog
  SystemVerilog RTL and UVM RAL model generators for RgGen
  ☆14Updated 2 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆46Updated this week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• aolofsson / POSH
  ☆43Updated 5 years ago
• Minres / RDL-Editor
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 9 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated 11 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• tenstorrent / cosim-arch-checker
  Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
  ☆16Updated last month