Alternatives and similar repositories for flgen:

Users that are interested in flgen are comparing it to the libraries listed below

• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆31Updated this week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• pulp-platform / svase
  ☆31Updated 2 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated 2 weeks ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated last week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated 2 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆37Updated 3 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆79Updated last week
• pulp-platform / cheshire-ihp130-o
  ☆33Updated 5 months ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆21Updated 8 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• Minres / RDL-Editor
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆24Updated last year
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆23Updated 2 weeks ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 7 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆55Updated 4 months ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆26Updated 10 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆44Updated 7 months ago
• 0x01be / rudder
  Learn, share and collaborate on ASIC design using open tools and technologies
  ☆13Updated 4 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆57Updated this week
• b224hisl / rioschip
  ☆33Updated 2 years ago