Filelist generator
☆20Feb 3, 2026Updated 3 weeks ago
Alternatives and similar repositories for flgen
Users that are interested in flgen are comparing it to the libraries listed below
Sorting:
- ☆33Nov 25, 2022Updated 3 years ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 7 years ago
- SystemVerilog file list pruner☆16Feb 18, 2026Updated last week
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Updated this week
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Dec 27, 2020Updated 5 years ago
- ☆37Sep 19, 2024Updated last year
- Fabric generator and CAD tools graphical frontend☆17Aug 5, 2025Updated 6 months ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- The Diderot language compiler☆15Mar 13, 2023Updated 2 years ago
- Basic Common Modules☆46Dec 13, 2025Updated 2 months ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Files and documentation for Pico-Dirty-Blaster Workshop☆20Jun 21, 2025Updated 8 months ago
- ☆21Jun 23, 2024Updated last year
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- A python script that converts between schematic file formats☆21Dec 15, 2011Updated 14 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 3 months ago
- RISC-V by VectorBlox☆18Dec 14, 2015Updated 10 years ago
- Generate UVM testbench framework template files with Python 3☆27Dec 23, 2019Updated 6 years ago
- Open hardware 48x 1000baseT + 2x 25G SFP28 Ethernet switch☆31Jul 5, 2025Updated 7 months ago
- A SystemVerilog source file pickler.☆60Oct 20, 2024Updated last year
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- ☆35Jan 23, 2026Updated last month
- ☆29Oct 20, 2019Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Open Processor Architecture☆26Apr 7, 2016Updated 9 years ago
- Making cocotb testbenches that bit easier☆37Updated this week
- ☆31Oct 2, 2023Updated 2 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆174Dec 29, 2025Updated 2 months ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- A modern schematic entry and simulation program☆84Feb 10, 2026Updated 2 weeks ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- ☆33Jan 7, 2025Updated last year
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- SpiceBind – spice inside HDL simulator☆56Jun 30, 2025Updated 8 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- EdgeCortix maintained and extended fork of Apache TVM compiler stack utilized by MERA framework. TVM is an open deep learning compiler st…☆11Dec 22, 2023Updated 2 years ago