Alternatives and similar repositories for flgen

Users that are interested in flgen are comparing it to the libraries listed below

• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated this week
• pezy-computing / pzbcm
  Basic Common Modules
  ☆46Updated last month
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated last week
• pulp-platform / svase
  ☆33Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆60Updated 2 weeks ago
• Silimate / prunefl
  SystemVerilog file list pruner
  ☆16Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 2 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• avidan-efody / pyreg
  Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
  ☆11Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated 2 weeks ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 7 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆49Updated 3 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆64Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago