Python bindings for slang, a library for compiling SystemVerilog
☆67Jan 18, 2025Updated last year
Alternatives and similar repositories for pyslang
Users that are interested in pyslang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog compiler and language services☆1,107Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆481Jun 10, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆471Jul 28, 2026Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆27Jul 25, 2026Updated 2 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated last year
- The UVM written in Python☆564Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆331Jun 30, 2025Updated last year
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆15Jun 30, 2026Updated last month
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- SystemVerilog linter☆388Nov 6, 2025Updated 9 months ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 3 months ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆797Jun 15, 2024Updated 2 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆57Aug 1, 2026Updated last week
- A SystemVerilog Language Server☆208Nov 30, 2025Updated 8 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,904Updated this week
- SystemVerilog to Verilog conversion☆747Mar 28, 2026Updated 4 months ago
- An abstraction library for interfacing EDA tools☆785Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆147Jul 5, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆137Nov 17, 2025Updated 8 months ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆152Jan 23, 2024Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆266Jul 22, 2026Updated 2 weeks ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆81Oct 22, 2024Updated last year
- datasheet generator☆31Jul 18, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆385Updated this week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆69Aug 18, 2021Updated 4 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆736Updated this week
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog language server☆582Jul 28, 2026Updated last week
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi…☆21May 8, 2024Updated 2 years ago
- SystemVerilog design elaborator into word-level netlist form☆246Updated this week
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆21May 12, 2025Updated last year
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year