Alternatives and similar repositories for pyslang

Users that are interested in pyslang are comparing it to the libraries listed below

• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated last month
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆118Updated 3 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated last week
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆73Updated this week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated last month
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆73Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆164Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆71Updated 3 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 11 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆176Updated 4 months ago
• accellera / uvm
  ☆60Updated 9 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆25Updated 4 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆60Updated last month
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆50Updated 4 years ago
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆53Updated 2 years ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 10 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last month
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆28Updated 3 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆75Updated 4 years ago
• svunit / svunit
  ☆207Updated 10 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year