Python bindings for slang, a library for compiling SystemVerilog
☆66Jan 18, 2025Updated last year
Alternatives and similar repositories for pyslang
Users that are interested in pyslang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog compiler and language services☆1,027Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆470Mar 30, 2026Updated last month
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Apr 5, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆459Apr 5, 2026Updated last month
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- The UVM written in Python☆537Apr 27, 2026Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆324Jun 30, 2025Updated 10 months ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- SystemVerilog linter☆381Nov 6, 2025Updated 6 months ago
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆789Jun 15, 2024Updated last year
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆54Mar 22, 2026Updated last month
- Running Python code in SystemVerilog☆72Jun 8, 2025Updated 11 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A SystemVerilog Language Server☆198Nov 30, 2025Updated 5 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- SystemVerilog frontend for Yosys☆218Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,834Mar 13, 2026Updated last month
- SystemVerilog to Verilog conversion☆725Mar 28, 2026Updated last month
- An abstraction library for interfacing EDA tools☆765Apr 24, 2026Updated 2 weeks ago
- ☆133Nov 17, 2025Updated 5 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆144Apr 9, 2026Updated last month
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆255Feb 22, 2026Updated 2 months ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆80Oct 22, 2024Updated last year
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆147Jan 23, 2024Updated 2 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆375Updated this week
- datasheet generator☆30Jul 18, 2025Updated 9 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆67Aug 18, 2021Updated 4 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆711Dec 14, 2025Updated 4 months ago
- SystemVerilog language server☆574Apr 2, 2026Updated last month
- A Python package for creating and solving constrained randomization problems.☆19Oct 14, 2024Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi…☆21May 8, 2024Updated 2 years ago
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆20May 12, 2025Updated 11 months ago
- A SystemVerilog source file pickler.☆61Oct 20, 2024Updated last year
- UVM 1.2 port to Python☆260Feb 9, 2025Updated last year
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- ☆25Dec 4, 2025Updated 5 months ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 4 months ago