Python bindings for slang, a library for compiling SystemVerilog
☆67Jan 18, 2025Updated last year
Alternatives and similar repositories for pyslang
Users that are interested in pyslang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog compiler and language services☆1,144Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆27Sep 11, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated last year
- The UVM written in Python☆570Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆332Jun 30, 2025Updated last year
- Open source RTL simulation acceleration on commodity hardware☆36Apr 13, 2023Updated 3 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆15Jun 30, 2026Updated 2 months ago
- Verilog AST☆19Dec 2, 2023Updated 2 years ago
- SystemVerilog linter☆393Nov 6, 2025Updated 10 months ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 4 months ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆801Jun 15, 2024Updated 2 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆57Aug 1, 2026Updated last month
- A SystemVerilog Language Server☆211Nov 30, 2025Updated 9 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,938Updated this week
- SystemVerilog to Verilog conversion☆753Aug 18, 2026Updated last month
- Template for a BTHome sensor in nRF52.☆12Mar 18, 2023Updated 3 years ago
- An abstraction library for interfacing EDA tools☆795Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Python packages providing a library for Verification Stimulus and Coverage☆148Updated this week
- ☆137Nov 17, 2025Updated 10 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆82Oct 22, 2024Updated last year
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆153Jan 23, 2024Updated 2 years ago
- datasheet generator☆31Sep 10, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆394Updated this week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆70Aug 18, 2021Updated 5 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆739Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- SystemVerilog language server☆585Sep 14, 2026Updated last week
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi…☆22May 8, 2024Updated 2 years ago
- SystemVerilog design elaborator into word-level netlist form☆250Updated this week
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆21May 12, 2025Updated last year