TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
☆602Updated this week
Alternatives and similar repositories for vscode-terosHDL:
Users that are interested in vscode-terosHDL are comparing it to the libraries listed below
- SystemVerilog to Verilog conversion☆604Updated this week
- Common SystemVerilog components☆590Updated last week
- lowRISC Style Guides☆400Updated 6 months ago
- Bus bridges and other odds and ends☆526Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,240Updated this week
- The UVM written in Python☆415Updated 2 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆389Updated last month
- VUnit is a unit testing framework for VHDL/SystemVerilog☆766Updated this week
- A huge VHDL library for FPGA development☆380Updated this week
- An abstraction library for interfacing EDA tools☆670Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆560Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,494Updated last month
- Open Logic FPGA Standard Library☆550Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- Verilog I2C interface for FPGA implementation☆591Updated 3 weeks ago
- A DDR3 memory controller in Verilog for various FPGAs☆426Updated 3 years ago
- SystemVerilog compiler and language services☆700Updated this week
- Verilog AXI stream components for FPGA implementation☆791Updated 3 weeks ago
- Test suite designed to check compliance with the SystemVerilog standard.☆309Updated this week
- cocotb: Python-based chip (RTL) verification☆1,922Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆989Updated this week
- FOSS Flow For FPGA☆376Updated 2 months ago
- 32-bit Superscalar RISC-V CPU☆972Updated 3 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆435Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,028Updated last month
- An open-source static random access memory (SRAM) compiler.☆883Updated 4 months ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆631Updated 2 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆421Updated 6 months ago
- A Linux-capable RISC-V multicore for and by the world☆669Updated 3 weeks ago
- Various HDL (Verilog) IP Cores☆760Updated 3 years ago