VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
☆729Dec 14, 2025Updated 7 months ago
Alternatives and similar repositories for vscode-terosHDL
Users that are interested in vscode-terosHDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- cocotb: Python-based chip (RTL) verification☆2,455Updated this week
- Style guide enforcement for VHDL☆247Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,895Updated this week
- ☆17Apr 20, 2023Updated 3 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆839May 14, 2026Updated 2 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Code generation tool for control and status registers☆463Jul 16, 2026Updated last week
- SystemVerilog compiler and language services☆1,093Updated this week
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 3 weeks ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Verilog/SystemVerilog support for VS Code☆380Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,440Jul 2, 2026Updated 3 weeks ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- VHDL 2008/93/87 simulator☆2,847Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Multi-platform nightly builds of open source digital design and verification tools☆1,608Updated this week
- HDL symbol generator☆205Feb 2, 2023Updated 3 years ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆995Updated this week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆265Jun 6, 2026Updated last month
- A huge VHDL library for FPGA and digital ASIC development☆476Updated this week
- A fast VHDL language server and analysis library written in Rust☆501Jul 13, 2026Updated last week
- The UVM written in Python☆561Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆454Apr 22, 2026Updated 3 months ago
- SystemVerilog linter☆388Nov 6, 2025Updated 8 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,631Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆467Updated this week
- SystemVerilog support in VS Code☆154Updated this week
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Repurposing existing HDL tools to help writing better code☆225Jun 21, 2026Updated last month
- Hardware Description Languages☆1,163Jul 9, 2026Updated 2 weeks ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 5 months ago
- Unit testing for cocotb☆174Apr 18, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Yosys Open SYnthesis Suite☆4,627Updated this week
- SystemVerilog to Verilog conversion☆741Mar 28, 2026Updated 3 months ago
- Digital timing diagram rendering engine☆3,448Jul 8, 2026Updated 2 weeks ago
- Web-based HDL diagramming tool☆86May 1, 2023Updated 3 years ago
- SystemVerilog language server☆582Updated this week
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- A curated list of awesome resources for HDL design and verification☆175Updated this week