Alternatives and similar repositories for vscode-terosHDL:

Users that are interested in vscode-terosHDL are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆372Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆590Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆388Updated 5 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,203Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆520Updated 2 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆401Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆776Updated 6 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆568Updated 4 years ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆385Updated this week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆479Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆369Updated last month
• alexforencich / verilog-uart
  Verilog UART
  ☆445Updated last year
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆758Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆663Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆955Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆740Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆550Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆405Updated 3 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆575Updated 7 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,239Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆235Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆871Updated last week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆198Updated 3 weeks ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆679Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆381Updated 2 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆943Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆455Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆473Updated 2 months ago