Alternatives and similar repositories for vscode-terosHDL:

Users that are interested in vscode-terosHDL are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆608Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆618Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆551Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆425Updated 7 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆423Updated 3 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,267Updated this week
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆427Updated 7 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆682Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆397Updated 2 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,276Updated 2 weeks ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated 3 weeks ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆802Updated 2 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆233Updated 11 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆485Updated 2 months ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆768Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆894Updated last month
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆903Updated this week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆586Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆388Updated 3 weeks ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,528Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆528Updated 3 weeks ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆604Updated 2 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆255Updated last year
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆779Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆330Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week