VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
☆737Aug 7, 2026Updated last week
Alternatives and similar repositories for vscode-terosHDL
Users that are interested in vscode-terosHDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- cocotb: Python-based chip (RTL) verification☆2,471Updated this week
- Style guide enforcement for VHDL☆249Jul 24, 2026Updated 3 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,910Updated this week
- ☆17Apr 20, 2023Updated 3 years ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆843Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Code generation tool for control and status registers☆465Jul 16, 2026Updated 3 weeks ago
- SystemVerilog compiler and language services☆1,115Updated this week
- An abstraction library for interfacing EDA tools☆788Updated this week
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Verilog/SystemVerilog support for VS Code☆383Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,450Updated this week
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- VHDL 2008/93/87 simulator☆2,864Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Multi-platform nightly builds of open source digital design and verification tools☆1,645Updated this week
- HDL symbol generator☆205Feb 2, 2023Updated 3 years ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆1,006Jul 23, 2026Updated 3 weeks ago
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆267Jul 30, 2026Updated 2 weeks ago
- A huge VHDL library for FPGA and digital ASIC development☆476Updated this week
- A fast VHDL language server and analysis library written in Rust☆504Updated this week
- The UVM written in Python☆566Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆457Apr 22, 2026Updated 3 months ago
- SystemVerilog linter☆388Nov 6, 2025Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,657Aug 5, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆481Jun 10, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆472Jul 28, 2026Updated 2 weeks ago
- SystemVerilog support in VS Code☆156Updated this week
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Repurposing existing HDL tools to help writing better code☆226Jun 21, 2026Updated last month
- Hardware Description Languages☆1,166Jul 9, 2026Updated last month
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 6 months ago
- Unit testing for cocotb☆174Apr 18, 2026Updated 3 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Yosys Open SYnthesis Suite☆4,672Updated this week
- SystemVerilog to Verilog conversion☆748Mar 28, 2026Updated 4 months ago
- Digital timing diagram rendering engine☆3,462Jul 8, 2026Updated last month
- Building and deploying container images for open source electronic design automation (EDA)☆123Oct 3, 2024Updated last year
- Web-based HDL diagramming tool☆86May 1, 2023Updated 3 years ago
- SystemVerilog language server☆583Jul 28, 2026Updated 2 weeks ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago