Alternatives and similar repositories for svls

Users that are interested in svls are comparing it to the libraries listed below

• dalance / svlint
  SystemVerilog linter
  ☆356Updated last month
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆449Updated 6 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆182Updated 4 months ago
• imc-trading / svlangserver
  ☆119Updated last year
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆422Updated 2 weeks ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆339Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆412Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆661Updated 2 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆653Updated 2 weeks ago
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆334Updated last week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,619Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆316Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆638Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆823Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆450Updated 2 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆420Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆523Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆600Updated 3 weeks ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆824Updated 2 months ago
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆403Updated 10 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 6 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆466Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆403Updated 7 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆586Updated 4 months ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆181Updated 3 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆257Updated last month
• SpinalHDL / NaxRiscv
  ☆295Updated 3 weeks ago