dalance / svlsLinks
SystemVerilog language server
☆517Updated this week
Alternatives and similar repositories for svls
Users that are interested in svls are comparing it to the libraries listed below
Sorting:
- SystemVerilog linter☆352Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆444Updated 4 months ago
- A SystemVerilog Language Server☆175Updated 3 months ago
- ☆115Updated last year
- Repurposing existing HDL tools to help writing better code☆214Updated last year
- ☆413Updated 2 weeks ago
- Test suite designed to check compliance with the SystemVerilog standard.☆333Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆399Updated this week
- A dependency management tool for hardware projects.☆311Updated last week
- Common SystemVerilog components☆634Updated last week
- SystemVerilog to Verilog conversion☆648Updated 3 weeks ago
- HDL support for VS Code☆328Updated this week
- SystemVerilog compiler and language services☆790Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆625Updated 3 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,588Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆587Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆510Updated 5 months ago
- lowRISC Style Guides☆440Updated last month
- Code generation tool for control and status registers☆406Updated last month
- SystemVerilog support in VS Code☆141Updated 4 months ago
- FOSS Flow For FPGA☆394Updated 6 months ago
- Verilog/SystemVerilog Syntax and Omni-completion☆397Updated 9 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆221Updated 3 weeks ago
- Bus bridges and other odds and ends☆572Updated 3 months ago
- SystemRDL 2.0 language compiler front-end☆255Updated last week
- Open source implementation of a Verilog formatter☆179Updated 3 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆461Updated last week
- A Linux-capable RISC-V multicore for and by the world☆712Updated 2 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆260Updated 2 months ago
- ☆577Updated this week