SystemVerilog language server
☆585Sep 14, 2026Updated this week
Alternatives and similar repositories for svls
Users that are interested in svls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog linter☆393Nov 6, 2025Updated 10 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 3 months ago
- A SystemVerilog Language Server☆210Nov 30, 2025Updated 9 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,938Updated this week
- ☆137Nov 17, 2025Updated 10 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog compiler and language services☆1,144Updated this week
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- Repurposing existing HDL tools to help writing better code☆227Jun 21, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆394Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,935Updated this week
- A fast VHDL language server and analysis library written in Rust☆510Updated this week
- Veryl: A Modern Hardware Description Language☆1,038Updated this week
- Verilog/SystemVerilog Syntax and Omni-completion☆424Aug 3, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog/SystemVerilog support for VS Code☆387Updated this week
- Open source implementation of a Verilog formatter☆187Jan 27, 2022Updated 4 years ago
- SystemVerilog to Verilog conversion☆753Aug 18, 2026Updated last month
- Common SystemVerilog components☆799Updated this week
- cocotb: Python-based chip (RTL) verification☆2,510Updated this week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆1,017Sep 3, 2026Updated 2 weeks ago
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆289Aug 31, 2026Updated 2 weeks ago
- Yosys Open SYnthesis Suite☆4,761Updated this week
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- An abstraction library for interfacing EDA tools☆795Updated this week
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated 2 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 2 months ago
- Icarus Verilog☆3,644Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,461Sep 12, 2026Updated last week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆739Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Chisel: A Modern Hardware Design Language☆4,786Sep 11, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,702Updated this week
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆548Sep 9, 2026Updated last week
- A Linux-capable RISC-V multicore for and by the world☆832Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆681Sep 8, 2026Updated last week
- Digital timing diagram rendering engine☆3,495Aug 31, 2026Updated 2 weeks ago