Alternatives and similar repositories for svls

Users that are interested in svls are comparing it to the libraries listed below

• dalance / svlint
  SystemVerilog linter
  ☆372Updated 2 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆457Updated 2 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆191Updated last month
• imc-trading / svlangserver
  ☆128Updated last month
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆221Updated last year
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆450Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆434Updated 4 months ago
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆346Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆354Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆693Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆682Updated 3 weeks ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆341Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆692Updated 3 weeks ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆915Updated this week
• rggen / rggen
  Code generation tool for control and status registers
  ☆439Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆473Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆557Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆632Updated 2 weeks ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,737Updated 2 weeks ago
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆412Updated last year
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆485Updated this week
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 10 months ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆183Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆618Updated 8 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• riscv-non-isa / riscv-arch-test
  ☆628Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆754Updated 2 months ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆890Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆312Updated 6 months ago