Alternatives and similar repositories for rust_hdl

Users that are interested in rust_hdl are comparing it to the libraries listed below

• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆211Updated 2 months ago
• dalance / svlint
  SystemVerilog linter
  ☆350Updated last week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆444Updated 3 months ago
• dalance / svls
  SystemVerilog language server
  ☆513Updated 2 weeks ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆399Updated last month
• nickg / nvc
  VHDL compiler and simulator
  ☆705Updated this week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆625Updated 2 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆391Updated 5 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆335Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆779Updated last month
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆209Updated last year
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆580Updated 4 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆696Updated last week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆242Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆395Updated last week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆307Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆639Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆328Updated this week
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆67Updated 2 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆175Updated 2 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated last week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆660Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆390Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆457Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆438Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆290Updated 2 weeks ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆275Updated 5 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆240Updated 8 months ago