Alternatives and similar repositories for rust_hdl:

Users that are interested in rust_hdl are comparing it to the libraries listed below

• dalance / svls
  SystemVerilog language server
  ☆505Updated last week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆436Updated 2 months ago
• dalance / svlint
  SystemVerilog linter
  ☆342Updated last month
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆334Updated 3 weeks ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆206Updated 3 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆397Updated 3 weeks ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆612Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆768Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆295Updated this week
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆207Updated 11 months ago
• nickg / nvc
  VHDL compiler and simulator
  ☆689Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆238Updated last week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆390Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆621Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆65Updated last month
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆282Updated last week
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆167Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆608Updated 3 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,280Updated 3 weeks ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆275Updated last year
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆234Updated 6 months ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆737Updated this week
• veryl-lang / veryl
  Veryl: A Modern Hardware Description Language
  ☆622Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆425Updated 7 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆552Updated 3 weeks ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,532Updated this week