Alternatives and similar repositories for rust_hdl

Users that are interested in rust_hdl are comparing it to the libraries listed below

• dalance / svls
  SystemVerilog language server
  ☆543Updated 3 weeks ago
• dalance / svlint
  SystemVerilog linter
  ☆364Updated last month
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆452Updated 8 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆332Updated this week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆225Updated 3 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆411Updated 9 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆659Updated last month
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆349Updated 3 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆410Updated last month
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆187Updated 6 months ago
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆69Updated 7 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆101Updated 5 months ago
• nickg / nvc
  VHDL compiler and simulator
  ☆750Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆250Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆793Updated 2 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆475Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆720Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆427Updated last month
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆346Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆295Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆600Updated 6 months ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆872Updated this week
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆595Updated 3 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆406Updated this week