VHDL-LS / rust_hdlLinks
A fast VHDL language server and analysis library written in Rust
☆421Updated 2 weeks ago
Alternatives and similar repositories for rust_hdl
Users that are interested in rust_hdl are comparing it to the libraries listed below
Sorting:
- SystemVerilog linter☆356Updated last month
- SystemVerilog language server☆524Updated 3 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆449Updated 5 months ago
- A dependency management tool for hardware projects.☆316Updated last month
- Style guide enforcement for VHDL☆216Updated last week
- FOSS Flow For FPGA☆403Updated 7 months ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆638Updated this week
- VHDL synthesis (based on ghdl)☆344Updated 3 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆402Updated 2 weeks ago
- VHDL Language Support for VSCode☆67Updated 5 months ago
- Repurposing existing HDL tools to help writing better code☆217Updated last year
- A SystemVerilog Language Server☆182Updated 4 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆229Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆407Updated last week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆245Updated 3 weeks ago
- VHDL compiler and simulator☆729Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆338Updated this week
- An abstraction library for interfacing EDA tools☆708Updated last month
- VUnit is a unit testing framework for VHDL/SystemVerilog☆786Updated 2 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆244Updated 10 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆466Updated 3 weeks ago
- A huge VHDL library for FPGA and digital ASIC development☆395Updated this week
- SystemVerilog to Verilog conversion☆659Updated 2 months ago
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- Language server based on ghdl☆97Updated 3 months ago
- Code generation tool for control and status registers☆419Updated 2 weeks ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆586Updated last month
- Bus bridges and other odds and ends☆586Updated 4 months ago
- SystemVerilog compiler and language services☆823Updated this week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆293Updated this week