Alternatives and similar repositories for synlig

Users that are interested in synlig are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆345Updated last week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆160Updated 3 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆201Updated last week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆299Updated 3 weeks ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆217Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆108Updated last week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆185Updated last week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated 2 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 3 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆147Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆162Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆156Updated 11 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated 2 weeks ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆143Updated last week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆128Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆116Updated 4 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆261Updated last month
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆280Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year