Alternatives and similar repositories for istyle-verilog-formatter:

Users that are interested in istyle-verilog-formatter are comparing it to the libraries listed below

• ericsonj / verilog-format
  Verilog formatter
  ☆189Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆137Updated last month
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆317Updated last week
• dalance / svlint
  SystemVerilog linter
  ☆337Updated 2 weeks ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆157Updated 3 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆231Updated 10 months ago
• imc-trading / svlangserver
  ☆109Updated 10 months ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆204Updated 9 months ago
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆249Updated 3 weeks ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆276Updated 5 years ago
• subbdue / systemverilog.io
  Code used in
  ☆180Updated 7 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆127Updated last year
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆132Updated 9 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆289Updated 3 weeks ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆429Updated 3 weeks ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆117Updated 9 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆174Updated 3 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆310Updated this week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• dalance / svls
  SystemVerilog language server
  ☆499Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆384Updated last week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated last month
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆250Updated last month
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆248Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆469Updated last month
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 7 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆402Updated 6 months ago