Alternatives and similar repositories for istyle-verilog-formatter

Users that are interested in istyle-verilog-formatter are comparing it to the libraries listed below

• ericsonj / verilog-format
  Verilog formatter
  ☆192Updated last year
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆324Updated this week
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆170Updated 2 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆139Updated 3 months ago
• dalance / svlint
  SystemVerilog linter
  ☆346Updated 2 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆297Updated 2 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆136Updated 11 months ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆208Updated last year
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆438Updated 3 months ago
• imc-trading / svlangserver
  ☆112Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆324Updated this week
• subbdue / systemverilog.io
  Code used in
  ☆186Updated 7 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated this week
• dalance / svls
  SystemVerilog language server
  ☆508Updated last month
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆148Updated 11 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 9 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆135Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆262Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆135Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated 3 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 4 months ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆124Updated 10 years ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆391Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆78Updated 7 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆194Updated 2 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆104Updated 2 years ago