thomasrussellmurphy / istyle-verilog-formatterLinks
Open source implementation of a Verilog formatter
☆181Updated 3 years ago
Alternatives and similar repositories for istyle-verilog-formatter
Users that are interested in istyle-verilog-formatter are comparing it to the libraries listed below
Sorting:
- Verilog formatter☆198Updated last year
- HDL support for VS Code☆336Updated last week
- SystemVerilog support in VS Code☆141Updated 7 months ago
- A SystemVerilog Language Server☆184Updated 5 months ago
- ☆119Updated last year
- Repurposing existing HDL tools to help writing better code☆217Updated last year
- A git-friendly Vivado wrapper☆236Updated last year
- SystemVerilog linter☆359Updated last week
- Code used in☆196Updated 8 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆140Updated last year
- ☆65Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆139Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆417Updated 2 weeks ago
- SystemVerilog language server☆530Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆342Updated this week
- Various caches written in Verilog-HDL☆126Updated 10 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated this week
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆100Updated 3 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆304Updated 2 months ago
- Labs to learn SpinalHDL☆149Updated last year
- SystemRDL 2.0 language compiler front-end☆261Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆449Updated 6 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆271Updated last week
- HTML & Js based VCD viewer☆62Updated last month
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- A simple, basic, formally verified UART controller☆310Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆216Updated last week
- UVM 1.2 port to Python☆253Updated 7 months ago