Open source implementation of a Verilog formatter
☆181Jan 27, 2022Updated 4 years ago
Alternatives and similar repositories for istyle-verilog-formatter
Users that are interested in istyle-verilog-formatter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog formatter☆203Mar 25, 2026Updated 3 weeks ago
- SystemVerilog linter☆380Nov 6, 2025Updated 5 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,817Mar 13, 2026Updated last month
- SystemVerilog language server☆572Apr 2, 2026Updated 2 weeks ago
- Verilog/SystemVerilog Syntax and Omni-completion☆414Oct 13, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- HDL support for VS Code☆366Updated this week
- Open source implementation of a Verilog formatter☆23Jun 18, 2020Updated 5 years ago
- SystemVerilog to Verilog conversion☆719Mar 28, 2026Updated 3 weeks ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 6 years ago
- Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.☆13Nov 15, 2021Updated 4 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated 2 months ago
- Beautify SystemVerilog code in VSCode through Verible☆23Mar 26, 2026Updated 3 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆251Updated this week
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Apr 5, 2026Updated 2 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆324Jun 30, 2025Updated 9 months ago
- Verilog (SystemVerilog) coding style☆42Jan 7, 2019Updated 7 years ago
- SystemVerilog syntax highlight/indent support in vim☆52Jul 10, 2024Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆371Updated this week
- Simple parser for extracting VHDL documentation☆73Jul 12, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆787Jun 15, 2024Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆470Mar 30, 2026Updated 3 weeks ago
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 3 years ago
- SystemVerilog compiler and language services☆1,000Updated this week
- Mastering FPGASIC Book☆18Oct 26, 2025Updated 5 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,546Apr 11, 2026Updated last week
- An abstraction library for interfacing EDA tools☆760Apr 1, 2026Updated 2 weeks ago
- Common SystemVerilog components☆736Updated this week
- ☆17Jun 5, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- draws an SVG schematic from a JSON netlist☆783Jan 25, 2024Updated 2 years ago
- Python package for writing Value Change Dump (VCD) files.☆133Nov 10, 2024Updated last year
- A Python package for creating and solving constrained randomization problems.☆19Oct 14, 2024Updated last year
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…☆34Nov 6, 2024Updated last year
- Icarus Verilog☆3,405Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year