imc-trading / svlangserverLinks
☆129Updated 2 months ago
Alternatives and similar repositories for svlangserver
Users that are interested in svlangserver are comparing it to the libraries listed below
Sorting:
- A SystemVerilog Language Server☆195Updated last month
- Repurposing existing HDL tools to help writing better code☆222Updated last year
- SystemVerilog language server☆558Updated last week
- SystemVerilog linter☆373Updated 2 months ago
- SystemVerilog grammar for tree-sitter☆113Updated last year
- SystemVerilog support in VS Code☆146Updated 11 months ago
- Language server based on ghdl☆102Updated 8 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated last year
- Open source implementation of a Verilog formatter☆183Updated 3 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆356Updated this week
- verilog filetype plugin to enable emacs verilog-mode autos☆25Updated 3 years ago
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆40Updated last year
- UVM 1.2 port to Python☆257Updated 11 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆435Updated 4 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆243Updated 4 months ago
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆279Updated 2 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆461Updated 2 months ago
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- SystemVerilog tree-sitter grammar☆43Updated 3 months ago
- A SystemVerilog language server based on the Slang library.☆104Updated this week
- A dependency management tool for hardware projects.☆342Updated last week
- Verilog Configurable Cache☆190Updated last week
- Code generation tool for control and status registers☆439Updated 2 weeks ago
- ☆109Updated last year
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- SystemRDL 2.0 language compiler front-end☆269Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆145Updated 2 weeks ago
- SystemVerilog synthesis tool☆225Updated 10 months ago
- HDL support for VS Code☆349Updated this week
- RISC-V Verification Interface☆136Updated last month