Alternatives and similar repositories for svlangserver

Users that are interested in svlangserver are comparing it to the libraries listed below

• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆193Updated 2 months ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆221Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆377Updated 3 months ago
• dalance / svls
  SystemVerilog language server
  ☆559Updated last month
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆148Updated 11 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 8 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆442Updated 5 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆357Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆259Updated last year
• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• gmlarumbe / tree-sitter-systemverilog
  SystemVerilog tree-sitter grammar
  ☆44Updated 3 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆463Updated 3 months ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆182Updated 4 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆344Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆246Updated 5 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆195Updated this week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated 2 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆310Updated last week
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆413Updated last year
• veripool / verilog-mode
  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  ☆281Updated 3 weeks ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• n-kremeris / verilator_basics
  ☆72Updated 2 years ago
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆443Updated last month
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆138Updated 2 weeks ago
• chipsalliance / uvm-verilator
  ☆114Updated 3 months ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆239Updated this week