Alternatives and similar repositories for veridian

Users that are interested in veridian are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆124Updated this week
• dalance / svlint
  SystemVerilog linter
  ☆367Updated 2 weeks ago
• dalance / svls
  SystemVerilog language server
  ☆548Updated 2 weeks ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆452Updated 2 weeks ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆335Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆425Updated 2 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆145Updated 9 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆111Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 2 months ago
• gmlarumbe / tree-sitter-systemverilog
  SystemVerilog tree-sitter grammar
  ☆41Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆347Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆218Updated 8 months ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆183Updated 3 years ago
• n-kremeris / verilator_basics
  ☆68Updated 2 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 10 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆186Updated this week
• mshr-h / vscode-verilog-hdl-support
  HDL support for VS Code
  ☆340Updated this week
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 6 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆170Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last month
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆440Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆281Updated last week
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆101Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆542Updated last month
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• riscv-software-src / riscof
  ☆93Updated 2 months ago