A SystemVerilog Language Server
☆199Nov 30, 2025Updated 5 months ago
Alternatives and similar repositories for veridian
Users that are interested in veridian are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog language server☆572Apr 2, 2026Updated last month
- SystemVerilog linter☆383Nov 6, 2025Updated 6 months ago
- ☆133Nov 17, 2025Updated 6 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,849Mar 13, 2026Updated 2 months ago
- SystemVerilog compiler and language services☆1,049Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆472Mar 30, 2026Updated 2 months ago
- Repurposing existing HDL tools to help writing better code☆221Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆256May 23, 2026Updated last week
- HDL support for VS Code☆368Updated this week
- SystemVerilog synthesis tool☆233Mar 10, 2025Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆66Jan 18, 2025Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆126May 21, 2026Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆327Jun 30, 2025Updated 10 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languag…☆481May 7, 2026Updated 3 weeks ago
- A Verilog IEEE 1364-2005 language server written in Nim.☆15Aug 25, 2022Updated 3 years ago
- Example of how to use UVM with Verilator☆46Apr 20, 2026Updated last month
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆715Dec 14, 2025Updated 5 months ago
- Logic circuit analysis and optimization☆49Feb 2, 2026Updated 3 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆376Updated this week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆975Apr 21, 2026Updated last month
- ☆97May 20, 2026Updated last week
- Description of Apple's LEAP ISA☆16Nov 21, 2022Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Web-based HDL diagramming tool☆83May 1, 2023Updated 3 years ago
- Nix template for the chisel-based industrial designing flows.☆57Apr 23, 2025Updated last year
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated 11 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- A simple digital waveform viewer with vi-like key bindings.☆145Mar 7, 2025Updated last year
- The UVM written in Python☆542May 18, 2026Updated last week
- SystemVerilog/Verilog support for vscode using Ctags☆38Sep 19, 2025Updated 8 months ago
- SystemVerilog to Verilog conversion☆730Mar 28, 2026Updated 2 months ago
- Veryl: A Modern Hardware Description Language☆941May 22, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A fast VHDL language server and analysis library written in Rust☆486Updated this week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆38Jan 26, 2026Updated 4 months ago
- Interpreter and compiler for the ISA specification language "Architecture Specification Language" (ASL)☆29Apr 30, 2026Updated 3 weeks ago
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- Integrated Circuit Layout☆62Feb 25, 2025Updated last year
- cocotb: Python-based chip (RTL) verification☆2,379May 22, 2026Updated last week
- WAL enables programmable waveform analysis.☆179Nov 10, 2025Updated 6 months ago