Alternatives and similar repositories for veridian:

Users that are interested in veridian are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆109Updated 10 months ago
• dalance / svlint
  SystemVerilog linter
  ☆341Updated last month
• dalance / svls
  SystemVerilog language server
  ☆504Updated last week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆433Updated last month
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆207Updated 10 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆137Updated 2 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆189Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆313Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆388Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆292Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated 3 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆56Updated 3 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆99Updated 5 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆175Updated 4 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆475Updated 2 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆150Updated last week
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆179Updated 3 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆601Updated this week
• chipsalliance / uvm-verilator
  ☆92Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆150Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆120Updated this week
• n-kremeris / verilator_basics
  ☆60Updated 2 years ago
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆12Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆131Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆123Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆176Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆145Updated 3 weeks ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆91Updated last month
• rggen / rggen
  Code generation tool for control and status registers
  ☆380Updated 2 months ago