dalance / svls-vscodeLinks
SystemVerilog language server client for Visual Studio Code
☆21Updated 2 years ago
Alternatives and similar repositories for svls-vscode
Users that are interested in svls-vscode are comparing it to the libraries listed below
Sorting:
- Basic Common Modules☆43Updated 2 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆62Updated 6 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- ☆97Updated last year
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆126Updated 3 weeks ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆56Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆83Updated 4 years ago
- Generate UVM register model from compiled SystemRDL input☆58Updated 11 months ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated last week
- Simple parser for extracting VHDL documentation☆71Updated last year
- RISC-V RV32IMAFC Core for MCU☆38Updated 6 months ago
- RISC-V Verification Interface☆100Updated 2 months ago
- Running Python code in SystemVerilog☆70Updated 2 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 10 months ago
- SystemVerilog/Verilog support for vscode☆32Updated 3 months ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆71Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated last month
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆68Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- Python interface for cross-calling with HDL☆34Updated this week
- Control and status register code generator toolchain☆142Updated 2 months ago
- ideas and eda software for vlsi design☆50Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago