dalance / svls-vscodeLinks
SystemVerilog language server client for Visual Studio Code
☆23Updated 2 years ago
Alternatives and similar repositories for svls-vscode
Users that are interested in svls-vscode are comparing it to the libraries listed below
Sorting:
- Basic Common Modules☆45Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- ☆110Updated last month
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- SystemVerilog/Verilog support for vscode using Ctags☆37Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- An Open-Source Design and Verification Environment for RISC-V☆85Updated 4 years ago
- Platform Level Interrupt Controller☆44Updated last year
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated 10 months ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- RISC-V RV32IMAFC Core for MCU☆40Updated 10 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 6 months ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆117Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆71Updated last week
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Generate UVM register model from compiled SystemRDL input☆60Updated 2 weeks ago
- Chisel Learning Journey☆111Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆131Updated 3 weeks ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆52Updated 4 months ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year