SystemVerilog support in VS Code
☆150Feb 18, 2025Updated last year
Alternatives and similar repositories for VSCode-SystemVerilog
Users that are interested in VSCode-SystemVerilog are comparing it to the libraries listed below
Sorting:
- HDL support for VS Code☆356Mar 15, 2026Updated last week
- Beautify SystemVerilog code in VSCode through Verible☆22Feb 28, 2026Updated 3 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,789Mar 13, 2026Updated last week
- SystemVerilog linter☆379Nov 6, 2025Updated 4 months ago
- IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…☆33Nov 6, 2024Updated last year
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- SystemVerilog plugin for Sublime Text☆49Sep 21, 2025Updated 6 months ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆702Dec 14, 2025Updated 3 months ago
- Render waveforms inside VSCode with WaveDrom☆38Feb 28, 2026Updated 3 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆467Nov 4, 2025Updated 4 months ago
- SystemVerilog compiler and language services☆985Updated this week
- ☆210Feb 28, 2026Updated 3 weeks ago
- SystemVerilog language server☆564Mar 9, 2026Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆320Jun 30, 2025Updated 8 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆368Updated this week
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆37Jan 21, 2015Updated 11 years ago
- ☆11Dec 15, 2023Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆451Mar 8, 2026Updated 2 weeks ago
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆83Mar 10, 2018Updated 8 years ago
- SystemVerilog/Verilog support for vscode using Ctags☆37Sep 19, 2025Updated 6 months ago
- ☆131Nov 17, 2025Updated 4 months ago
- Pulp virtual platform☆24Jul 16, 2025Updated 8 months ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Mar 6, 2022Updated 4 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆653Jan 19, 2026Updated 2 months ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,439Updated this week
- cocotb: Python-based chip (RTL) verification☆2,284Mar 13, 2026Updated last week
- The UVM written in Python☆510Mar 9, 2026Updated last week
- Atom Hardware IDE☆13May 4, 2021Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Feb 23, 2026Updated 3 weeks ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 2 months ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated last year
- A SystemVerilog Language Server☆194Nov 30, 2025Updated 3 months ago
- ☆21Mar 12, 2026Updated last week