pezy-computing / pzbcm

Related projects: ⓘ

• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆66Updated 4 months ago
• efabless / sky130_sram_macros_old
  ☆35Updated 2 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆34Updated 2 weeks ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 4 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆40Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆49Updated 9 months ago
• thiemchu / rvcorep
  ☆9Updated 2 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆29Updated 3 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆31Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆48Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆22Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 3 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆21Updated last year
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆24Updated 2 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆56Updated 3 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆44Updated 7 months ago
• pulp-platform / axi_llc
  ☆17Updated last week
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 4 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆28Updated 6 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 7 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆34Updated 4 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆29Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆102Updated 2 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆23Updated 4 months ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆35Updated 2 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆66Updated last year
• RIOSMPW / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆38Updated 4 months ago