pezy-computing / pzbcm
Basic Common Modules
☆34Updated last week
Related projects ⓘ
Alternatives and complementary repositories for pzbcm
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- SystemVerilog language server client for Visual Studio Code☆20Updated last year
- RISC-V RV32IMAFC Core for MCU☆35Updated 2 months ago
- ☆22Updated last year
- ☆36Updated 2 years ago
- An automatic clock gating utility☆43Updated 4 months ago
- YosysHQ SVA AXI Properties☆32Updated last year
- Automatic SystemVerilog linting in github actions with the help of Verible☆28Updated 3 weeks ago
- A SystemVerilog source file pickler.☆51Updated last month
- ☆75Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated 6 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- ☆9Updated 2 years ago
- ☆21Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆34Updated last month
- ☆39Updated 4 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆29Updated 3 years ago
- slang-based frontend for Yosys☆43Updated this week
- Equivalence checking with Yosys☆31Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- Chisel Cheatsheet☆31Updated last year
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- 10G Ethernet MAC implementation☆21Updated 4 years ago
- RISC-V Nox core☆61Updated 3 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- The multi-core cluster of a PULP system.☆56Updated last week