Alternatives and similar repositories for pyuvm

Users that are interested in pyuvm are comparing it to the libraries listed below

• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆288Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆460Updated 3 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆426Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 8 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆571Updated 3 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆281Updated 3 years ago
• svunit / svunit
  ☆206Updated 7 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆323Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆432Updated 3 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆199Updated 8 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆382Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆589Updated 5 months ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆261Updated 12 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆661Updated 2 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆423Updated 3 weeks ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆832Updated 7 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆344Updated this week
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated this week
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆221Updated 2 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆611Updated last week
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆406Updated last week
• accellera-official / uvm-core
  ☆98Updated last year
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆393Updated last year
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆155Updated 5 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆416Updated last month
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆203Updated 4 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆522Updated 3 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆162Updated 3 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year