Alternatives and similar repositories for pyuvm:

Users that are interested in pyuvm are comparing it to the libraries listed below

• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆226Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆247Updated 10 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆371Updated 7 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆560Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• svunit / svunit
  ☆194Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆511Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆542Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆242Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆384Updated 4 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆769Updated 5 months ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆254Updated 2 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆180Updated last year
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆236Updated 11 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆126Updated last year
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆180Updated 7 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆277Updated 2 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆196Updated 3 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆355Updated last week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆153Updated 3 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated last week
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆506Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆294Updated 9 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆380Updated last month
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆350Updated last month
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,188Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆285Updated 4 months ago
• raysalemi / Python4RTLVerification
  ☆130Updated 2 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆585Updated last month
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆274Updated 5 years ago