chipsalliance / UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆208Updated 3 months ago
Alternatives and similar repositories for UHDM:
Users that are interested in UHDM are comparing it to the libraries listed below
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆381Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆306Updated this week
- SystemVerilog synthesis tool☆177Updated this week
- SystemRDL 2.0 language compiler front-end☆244Updated last month
- UVM 1.2 port to Python☆248Updated last week
- Control and status register code generator toolchain☆112Updated last month
- Fabric generator and CAD tools☆159Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆141Updated 8 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆116Updated 4 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆265Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆288Updated 5 months ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆200Updated this week
- FuseSoC standard core library☆125Updated 2 weeks ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆196Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆454Updated this week
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆159Updated 2 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆108Updated last year
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆275Updated 5 years ago
- SystemVerilog support in VS Code☆133Updated last month
- A complete open-source design-for-testing (DFT) Solution☆145Updated 3 months ago
- VeeR EL2 Core☆263Updated this week
- FPGA tool performance profiling☆102Updated 11 months ago
- A dependency management tool for hardware projects.☆280Updated 2 weeks ago
- ☆195Updated 3 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆425Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆424Updated last week
- Control and Status Register map generator for HDL projects☆109Updated this week