Alternatives and similar repositories for hdl_checker

Users that are interested in hdl_checker are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆128Updated last month
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆191Updated last month
• dalance / svls
  SystemVerilog language server
  ☆556Updated 2 weeks ago
• dalance / svlint
  SystemVerilog linter
  ☆372Updated 2 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 7 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆239Updated 4 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆432Updated 4 months ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆229Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆352Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆118Updated 3 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆268Updated last month
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 6 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 10 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 10 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆457Updated 2 months ago
• svunit / svunit
  ☆207Updated 10 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆164Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 2 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆73Updated last year
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆338Updated this week
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated 11 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 3 weeks ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆183Updated 3 years ago
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆449Updated last week
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆20Updated last week
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆245Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆435Updated 2 weeks ago