Alternatives and similar repositories for hdl_checker

Users that are interested in hdl_checker are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆120Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆364Updated last month
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆187Updated 6 months ago
• dalance / svls
  SystemVerilog language server
  ☆543Updated 3 weeks ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆101Updated 5 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆225Updated 3 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• suoto / vim-hdl
  Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
  ☆60Updated 4 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆346Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 5 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆263Updated last month
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆109Updated 11 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 8 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last month
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆452Updated 7 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 3 weeks ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆332Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆216Updated 7 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 9 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆143Updated 8 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆427Updated last month
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• kevinpt / symbolator
  HDL symbol generator
  ☆195Updated 2 years ago
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• svunit / svunit
  ☆208Updated 7 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆306Updated 4 months ago