suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
☆200Updated 8 months ago
Alternatives and similar repositories for hdl_checker:
Users that are interested in hdl_checker are comparing it to the libraries listed below
- A SystemVerilog Language Server☆154Updated last month
- SystemVerilog language server☆492Updated this week
- ☆106Updated 8 months ago
- SystemVerilog linter☆334Updated last month
- Language server based on ghdl☆91Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆209Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆381Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆306Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆426Updated 2 weeks ago
- Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)☆60Updated 3 years ago
- Style guide enforcement for VHDL☆198Updated 3 weeks ago
- SystemVerilog synthesis tool☆177Updated this week
- UVM 1.2 port to Python☆248Updated last week
- Control and status register code generator toolchain☆112Updated 2 months ago
- SystemVerilog grammar for tree-sitter☆96Updated 3 months ago
- Experimental flows using nextpnr for Xilinx devices☆225Updated 4 months ago
- SystemRDL 2.0 language compiler front-end☆245Updated last month
- ☆372Updated last month
- ☆195Updated last month
- Verilog/SystemVerilog Syntax and Omni-completion☆374Updated 4 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆108Updated last year
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆202Updated this week
- A huge VHDL library for FPGA development☆372Updated this week
- Code generation tool for control and status registers☆363Updated this week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆275Updated 5 years ago
- A git-friendly Vivado wrapper☆225Updated 9 months ago
- SystemVerilog support in VS Code☆133Updated this week
- A dependency management tool for hardware projects.☆280Updated 3 weeks ago
- AXI interface modules for Cocotb☆233Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆116Updated 4 months ago