Alternatives and similar repositories for hdl_checker

Users that are interested in hdl_checker are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆119Updated last year
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆98Updated 4 months ago
• dalance / svlint
  SystemVerilog linter
  ☆359Updated last week
• dalance / svls
  SystemVerilog language server
  ☆530Updated this week
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆184Updated 5 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆232Updated 2 weeks ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆219Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆417Updated 2 weeks ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆282Updated 5 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆342Updated this week
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆108Updated 10 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆194Updated 2 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆261Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆422Updated last week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆322Updated 2 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆63Updated 8 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 7 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• svunit / svunit
  ☆206Updated 6 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 7 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆449Updated 6 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆236Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated this week
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆422Updated last month
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆304Updated 2 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 6 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆137Updated last year
• themperek / cocotb-test
  Unit testing for cocotb
  ☆162Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated 2 months ago