Repurposing existing HDL tools to help writing better code
☆227Jun 21, 2026Updated 2 months ago
Alternatives and similar repositories for hdl_checker
Users that are interested in hdl_checker are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)☆61Jun 1, 2021Updated 5 years ago
- A fast VHDL language server and analysis library written in Rust☆507Updated this week
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- A Sphinx domain providing VHDL language support.☆21Jul 11, 2026Updated last month
- VHDL related news.☆27Updated this week
- Language server based on ghdl☆103Aug 1, 2026Updated last month
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆332Jun 30, 2025Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆70Feb 16, 2026Updated 6 months ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Jun 23, 2026Updated 2 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog language server☆584Aug 25, 2026Updated last week
- ☆33Jul 15, 2026Updated last month
- ☆137Nov 17, 2025Updated 9 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆123Updated this week
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- An abstract language model of VHDL written in Python.☆65Aug 25, 2026Updated last week
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 6 months ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A SystemVerilog Language Server☆209Nov 30, 2025Updated 9 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆845Aug 13, 2026Updated 3 weeks ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 11 months ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆70Jul 29, 2026Updated last month
- A curated list of awesome resources for HDL design and verification☆176Aug 28, 2026Updated last week
- HDL symbol generator☆205Feb 2, 2023Updated 3 years ago
- Virtual development board for HDL design☆43Mar 31, 2023Updated 3 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,928Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Style guide enforcement for VHDL☆253Jul 24, 2026Updated last month
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated 3 months ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- A JSON library implemented in VHDL.☆87Jul 13, 2026Updated last month
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆17Apr 10, 2025Updated last year