ic-lab-duth / FusedGCN4HLSLinks
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
☆22Updated 2 years ago
Alternatives and similar repositories for FusedGCN4HLS
Users that are interested in FusedGCN4HLS are comparing it to the libraries listed below
Sorting:
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- An HBM FPGA based SpMV Accelerator☆13Updated 9 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 3 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆10Updated 2 years ago
- ☆35Updated 4 years ago
- ☆16Updated 2 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- NeuraChip Accelerator Simulator☆13Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- ☆4Updated 4 years ago
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- ☆29Updated 6 years ago
- ☆35Updated 3 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆25Updated last year
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆71Updated 2 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- ☆13Updated 4 years ago