Alternatives and similar repositories for FusedGCN4HLS

Users that are interested in FusedGCN4HLS are comparing it to the libraries listed below

• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆10Updated 5 years ago
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆13Updated 10 months ago
• sharc-lab / DGNN-Booster
  ☆16Updated 2 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆23Updated 8 months ago
• jasonlin316 / GCN-Inference-Acceleration-HLS
  An end-to-end GCN inference accelerator written in HLS
  ☆19Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆93Updated 9 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆80Updated 11 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆50Updated 8 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 3 months ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆28Updated 2 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 3 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆58Updated 3 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• SFU-HiAccel / CHIP-KNN
  [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
  ☆18Updated last year
• gicLAB / SECDA
  ☆24Updated 2 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆4Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated last week
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆13Updated last year
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆14Updated last year
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago