Alternatives and similar repositories for usb-test-suite-cocotb-usb

Users that are interested in usb-test-suite-cocotb-usb are comparing it to the libraries listed below

• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 9 months ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 3 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 3 years ago
• efabless / caravel-lite
  ☆17Updated 9 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• buttercutter / noc
  A simple spidergon network-on-chip with wormhole switching feature
  ☆12Updated 4 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated 2 weeks ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆82Updated 5 years ago
• bobbl / rudolv
  RISC-V processor
  ☆31Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last month
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 6 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 6 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 4 years ago
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆29Updated 6 years ago
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆16Updated 3 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• verilog-to-routing / libsdcparse
  ☆12Updated 5 years ago