Industry standard I/O for nMigen
☆12Apr 23, 2020Updated 5 years ago
Alternatives and similar repositories for nmigen-stdio
Users that are interested in nmigen-stdio are comparing it to the libraries listed below
Sorting:
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 5 years ago
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- A configurable USB 2.0 device core☆32Jun 12, 2020Updated 5 years ago
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- ☆12Aug 25, 2019Updated 6 years ago
- There are many RISC V projects on iCE40. This one is mine.☆14Jun 25, 2020Updated 5 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45May 25, 2025Updated 9 months ago
- ☆44Mar 12, 2025Updated 11 months ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- ☆15Oct 24, 2019Updated 6 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Oct 31, 2023Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- PCIe to .1 inch header breakout☆11Sep 14, 2020Updated 5 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- Bootloader for Fomu☆105Dec 31, 2022Updated 3 years ago
- reverse engineering the canon 5D mark II (5D2) image sensor☆33May 27, 2025Updated 9 months ago
- IceCore Ice40 HX based modular core☆47Jan 23, 2021Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- Verilog Examples and WebFPGA Standard Library☆11Nov 25, 2019Updated 6 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆13Sep 27, 2018Updated 7 years ago
- Utilities for working with a Wishbone bus in an embedded device☆47Aug 29, 2025Updated 6 months ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated 2 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 5 years ago
- VexRiscv-SMP integration test with LiteX.☆26Nov 16, 2020Updated 5 years ago
- 360nosc0pe Yocto build environment☆12Aug 27, 2018Updated 7 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago