ehw-fit / approx-fpgasLinks
Approximate arithmetic circuits for FPGAs
☆12Updated 5 years ago
Alternatives and similar repositories for approx-fpgas
Users that are interested in approx-fpgas are comparing it to the libraries listed below
Sorting:
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- ☆27Updated 5 years ago
- ☆10Updated last year
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- sram/rram/mram.. compiler☆37Updated last year
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- SRAM☆22Updated 4 years ago
- NoC based MPSoC☆11Updated 11 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆30Updated 2 weeks ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- FPU Generator☆20Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆28Updated 4 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- CNN accelerator☆27Updated 8 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- ☆16Updated 4 years ago
- ☆11Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago