ehw-fit / approx-fpgas
Approximate arithmetic circuits for FPGAs
☆11Updated 5 years ago
Alternatives and similar repositories for approx-fpgas
Users that are interested in approx-fpgas are comparing it to the libraries listed below
Sorting:
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- ☆27Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 11 years ago
- SRAM☆22Updated 4 years ago
- CNN accelerator☆27Updated 7 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- FPU Generator☆20Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆27Updated 2 months ago
- WISHBONE Interconnect☆11Updated 7 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- Open Source PHY v2☆28Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- ☆10Updated last year
- sram/rram/mram.. compiler☆33Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- ☆19Updated 10 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆33Updated 3 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Ratatoskr NoC Simulator☆25Updated 4 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 11 months ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 11 months ago