Alternatives and similar repositories for DaVE

Users that are interested in DaVE are comparing it to the libraries listed below

• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• aolofsson / POSH
  ☆44Updated 5 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆23Updated 5 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆47Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆67Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆21Updated 2 weeks ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆59Updated 2 weeks ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆38Updated 4 years ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆38Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆32Updated this week
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆26Updated 4 months ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆19Updated 2 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 3 weeks ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆48Updated last year
• StanfordVLSI / FP-Gen
  FPU Generator
  ☆20Updated 4 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago