Alternatives and similar repositories for DaVE

Users that are interested in DaVE are comparing it to the libraries listed below

• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆41Updated last year
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆23Updated 6 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆47Updated this week
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated 5 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated 11 months ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• mabrains / sky130_klayout_pdk
  Skywater 130nm Klayout Device Generators PDK
  ☆31Updated 11 months ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 4 months ago
• stineje / sky130_cds
  This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Proce…
  ☆23Updated last year
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆38Updated 2 years ago
• shalan / AD_SAR_ADC
  Digital Standard Cells based SAR ADC
  ☆14Updated 3 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆20Updated 7 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 11 months ago