Alternatives and similar repositories for DaVE

Users that are interested in DaVE are comparing it to the libraries listed below

• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆47Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 3 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆24Updated 5 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆19Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆32Updated 2 weeks ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆38Updated 4 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• avidan-efody / pyreg
  Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
  ☆11Updated 3 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated last month
• SpinalHDL / CocotbLib
  ☆18Updated 5 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆38Updated 4 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆31Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆72Updated last year
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated 3 weeks ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆15Updated 8 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆26Updated 6 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆63Updated 2 weeks ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆22Updated 2 months ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 4 years ago