StanfordVLSI / Genesis2Links
A home for Genesis2 sources.
☆43Updated 5 months ago
Alternatives and similar repositories for Genesis2
Users that are interested in Genesis2 are comparing it to the libraries listed below
Sorting:
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆73Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- Next generation CGRA generator☆118Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- ☆67Updated 2 years ago
- The Task Parallel System Composer (TaPaSCo)☆115Updated last week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Virtio implementation in SystemVerilog☆48Updated 7 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- SoCRocket - Core Repository☆38Updated 8 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- ☆88Updated 2 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- ☆82Updated last year