Alternatives and similar repositories for Genesis2

Users that are interested in Genesis2 are comparing it to the libraries listed below

• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆49Updated 9 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆67Updated 9 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆105Updated last year
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated last month
• socrocket / core
  SoCRocket - Core Repository
  ☆37Updated 8 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• oprecomp / DDR4_controller
  ☆59Updated 4 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆46Updated 3 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆63Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• intel / aib-phy-hardware
  ☆66Updated 2 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆55Updated 2 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 2 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆41Updated last month
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 8 months ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 8 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 4 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago