StanfordVLSI / Genesis2
A home for Genesis2 sources.
☆38Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for Genesis2
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆48Updated 4 years ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- Next generation CGRA generator☆106Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- ☆66Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- ☆75Updated last year
- SoCRocket - Core Repository☆33Updated 7 years ago
- ☆48Updated 3 years ago
- ☆30Updated last year
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Verilog Content Addressable Memory Module☆102Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆117Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆34Updated 8 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆44Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- ☆67Updated 10 years ago