StanfordVLSI / Genesis2Links
A home for Genesis2 sources.
☆42Updated last week
Alternatives and similar repositories for Genesis2
Users that are interested in Genesis2 are comparing it to the libraries listed below
Sorting:
- Next generation CGRA generator☆112Updated last week
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆69Updated 10 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆48Updated 9 years ago
- Project repo for the POSH on-chip network generator☆48Updated 4 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆68Updated this week
- ☆86Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆84Updated last month
- ☆66Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated last month
- OmniXtend cache coherence protocol☆82Updated last month
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last month
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆57Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated this week
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 5 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆160Updated last month