hngenc / stellarLinks
☆32Updated last year
Alternatives and similar repositories for stellar
Users that are interested in stellar are comparing it to the libraries listed below
Sorting:
- ☆60Updated 7 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆71Updated 7 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆72Updated last year
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆61Updated 3 months ago
- ☆16Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆75Updated 6 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆63Updated 4 months ago
- ☆53Updated 4 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆65Updated 2 weeks ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆70Updated last week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- ☆14Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- An integrated CGRA design framework☆91Updated 7 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆10Updated 2 years ago
- agile hardware-software co-design☆52Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago