An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics
☆15Jun 28, 2026Updated this week
Alternatives and similar repositories for bfg
Users that are interested in bfg are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆14Jan 15, 2024Updated 2 years ago
- ☆16Jan 25, 2026Updated 5 months ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆25Feb 15, 2024Updated 2 years ago
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- Interchange formats for chip design.☆39Feb 15, 2026Updated 4 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- ☆15May 24, 2025Updated last year
- Primary GIT Repository for the Zephyr Project☆13Updated this week
- Bitstream Fault Analysis Tool☆16Jul 17, 2023Updated 2 years ago
- Python interface to FPGA interchange format☆41Oct 19, 2022Updated 3 years ago
- Bulk scrape and download datasheets from various vendors (insult)☆14Aug 10, 2021Updated 4 years ago
- IRSIM switch-level simulator for digital circuits☆37Nov 13, 2025Updated 7 months ago
- SystemVerilog file list pruner☆19Mar 2, 2026Updated 3 months ago
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆47Apr 9, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- converts catgirls to gds files☆15May 24, 2021Updated 5 years ago
- RFCs for changes to the Amaranth language and standard components☆18May 3, 2026Updated last month
- nextpnr portable FPGA place and route tool☆21Aug 21, 2024Updated last year
- A configurable SRAM generator☆64May 15, 2026Updated last month
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆18Mar 28, 2025Updated last year
- Analyze experimental data with Programming by Navigation☆17Updated this week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 4 months ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 19, 2026Updated 3 months ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆41Jun 10, 2021Updated 5 years ago
- ☆16Jun 13, 2021Updated 5 years ago
- ☆15Dec 9, 2025Updated 6 months ago
- Low level arithmetic primitives in RTL☆25Apr 3, 2020Updated 6 years ago
- ILP SAT Detailed Router☆13Apr 14, 2020Updated 6 years ago
- FOSSi Foundation Website☆19Oct 5, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆18Jun 22, 2026Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆130Jul 22, 2021Updated 4 years ago
- A steam era route for Open Rails Train Simulator. Features the Bournemouth UK line timetable☆13Feb 8, 2025Updated last year
- Native Rust implementation of the FST waveform format from GTKWave.☆14Jun 4, 2026Updated 3 weeks ago
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆15Nov 15, 2022Updated 3 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago