Alternatives and similar repositories for bfg

Users that are interested in bfg are comparing it to the libraries listed below

• snishizawa / libretto
  Characterizer
  ☆30Updated last month
• rahulk29 / sram22
  A configurable SRAM generator
  ☆54Updated last month
• ieee-ceda-datc / datc-rdf-calibrations
  ☆18Updated 10 months ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆22Updated 5 months ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆32Updated 4 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆54Updated 2 months ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆10Updated 3 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• AsFigo / svck
  ☆14Updated 3 months ago
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆19Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆51Updated 2 years ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆44Updated 6 months ago
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆15Updated 2 years ago
• FPGA-Research / FABulator
  Fabric generator and CAD tools graphical frontend
  ☆14Updated last month
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆43Updated this week
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆37Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated 2 weeks ago
• heyfey / sv-pathfinder
  VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…
  ☆24Updated 2 weeks ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated last month
• idea-fasoc / fasoc
  ☆55Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆26Updated 2 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆24Updated this week
• StefanSchippers / xschem-gaw
  gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms
  ☆15Updated 5 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year