growly / bfgLinks
An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
☆11Updated this week
Alternatives and similar repositories for bfg
Users that are interested in bfg are comparing it to the libraries listed below
Sorting:
- Characterizer☆28Updated last month
- ☆14Updated last month
- A configurable SRAM generator☆53Updated last week
- ☆18Updated 8 months ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated 2 weeks ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Open-source PDK version manager☆17Updated 2 weeks ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated last month
- ☆32Updated 6 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆42Updated 4 months ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 4 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆14Updated 3 months ago
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 3 months ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- An automatic clock gating utility☆50Updated 3 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 3 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆35Updated this week
- ☆37Updated 3 years ago
- Open source process design kit for 28nm open process☆59Updated last year
- Interchange formats for chip design.☆31Updated 2 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- SystemVerilog Linter based on pyslang☆31Updated 2 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- Bitstream Fault Analysis Tool☆14Updated last year
- Open Source PHY v2☆29Updated last year
- SpiceBind – spice inside HDL simulator☆19Updated 2 weeks ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago