laforest / OctavoLinks
Verilog FPGA Parts Library. Old Octavo soft-CPU project.
☆75Updated 6 years ago
Alternatives and similar repositories for Octavo
Users that are interested in Octavo are comparing it to the libraries listed below
Sorting:
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- OpenFPGA☆34Updated 7 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆30Updated 7 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Yosys Plugins☆22Updated 6 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- iDEA FPGA Soft Processor☆16Updated 9 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- a playground for xilinx zynq fpga experiments☆49Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated last week
- mantle library☆44Updated 3 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Python interface to FPGA interchange format☆41Updated 3 years ago