Alternatives and similar repositories for XilinxUnisimLibrary:

Users that are interested in XilinxUnisimLibrary are comparing it to the libraries listed below

• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 9 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated this week
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆46Updated 8 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆87Updated 5 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆85Updated 9 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• oprecomp / DDR4_controller
  ☆54Updated 4 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 11 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆54Updated 2 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆91Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated 2 months ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 6 months ago
• pieter3d / simview
  ☆77Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago