chipsalliance / f4pga-bitstream-viewer

Related projects ⓘ

Alternatives and complementary repositories for f4pga-bitstream-viewer

• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆11Updated 4 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆20Updated 4 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆15Updated last year
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated 10 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆12Updated last year
• xobs / lxbuildenv
  Simplified environment for litex
  ☆13Updated 4 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• xobs / spibone
  Wishbone bridge over SPI
  ☆11Updated 4 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• albaEDA / Nirah
  Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…
  ☆12Updated 5 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 5 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆36Updated last year
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 6 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated 3 weeks ago
• daveshah1 / nextpnr
  nextpnr portable FPGA place and route tool
  ☆12Updated 3 years ago
• FPGAwars / toolchain-icestorm
  Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
  ☆38Updated 2 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• rohitk-singh / usb-device
  USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
  ☆11Updated 7 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 6 months ago
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆24Updated 3 years ago