A bit-serial CPU
☆20Sep 29, 2019Updated 6 years ago
Alternatives and similar repositories for seqpu
Users that are interested in seqpu are comparing it to the libraries listed below
Sorting:
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆18Apr 6, 2022Updated 3 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Jun 25, 2020Updated 5 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- Alliance VLSI CAD Tools (LIP6)☆20Dec 11, 2025Updated 3 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- ☆12Jun 4, 2021Updated 4 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆63Feb 24, 2026Updated 3 weeks ago
- Stencil with Optimized Dataflow Architecture☆12Feb 27, 2024Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Jan 21, 2025Updated last year
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 7 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated last month
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21May 20, 2020Updated 5 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Oct 24, 2023Updated 2 years ago
- wavedrom to verilog converter☆17Sep 14, 2021Updated 4 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆13Sep 27, 2018Updated 7 years ago
- ☆18Jul 9, 2025Updated 8 months ago
- ☆17Nov 25, 2017Updated 8 years ago
- A small, fast, integer-only texture mapped software renderer optimized for a Motorola 68000 processor.☆25Sep 3, 2022Updated 3 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Nov 2, 2025Updated 4 months ago
- ☆10Oct 15, 2021Updated 4 years ago
- 360nosc0pe Yocto build environment☆12Aug 27, 2018Updated 7 years ago
- Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…☆102Jan 12, 2021Updated 5 years ago
- Icarus SIMBUS☆20Nov 6, 2019Updated 6 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆17Dec 4, 2020Updated 5 years ago