pepijndevos / seqpu

Related projects: ⓘ

• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆26Updated last week
• trabucayre / quickfeather-notes
  Notes, scripts and apps to quickfeather board
  ☆10Updated 2 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆46Updated 8 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆33Updated 5 months ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆15Updated last year
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆42Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆19Updated 2 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆15Updated last year
• mballance / fwrisc-s
  ☆9Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆30Updated 4 months ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• ZipCPU / zipversa
  A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
  ☆13Updated 4 years ago
• awygle / waggle
  Rust proof-of-concept for GPU waveform rendering
  ☆13Updated 4 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆35Updated 6 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆34Updated last year
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆18Updated 7 years ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆13Updated 3 years ago
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆24Updated last year
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆20Updated 5 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated 8 months ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 11 months ago
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆12Updated 5 months ago