ganeshgore / spydrnet-physicalLinks
This is a SpyDrNet Plugin for a physical design related transformations
☆13Updated last month
Alternatives and similar repositories for spydrnet-physical
Users that are interested in spydrnet-physical are comparing it to the libraries listed below
Sorting:
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆25Updated 4 years ago
- Cross EDA Abstraction and Automation☆39Updated this week
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- Import and export IP-XACT XML register models☆35Updated 3 weeks ago
- IP-XACT XML binding library☆16Updated 9 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆31Updated last year
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Python interface for cross-calling with HDL☆34Updated last month
- Generates a SystemVerilog assertion interface for a given SV RTL design☆18Updated 3 months ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 4 months ago
- LAYout with Gridded Objects☆29Updated 5 years ago
- ☆18Updated 8 months ago
- Running Python code in SystemVerilog☆70Updated last month
- Online documentation can be found at https://minres.github.io/SCViewer/☆16Updated last year
- hardware library for hwt (= ipcore repo)☆40Updated this week
- ☆44Updated 5 years ago
- Provides automation scripts for building BFMs☆16Updated 3 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- Open source process design kit for 28nm open process☆59Updated last year
- Contains examples to start with Kactus2.☆19Updated 11 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆62Updated 3 weeks ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆15Updated 6 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated 2 weeks ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆29Updated this week
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated 3 weeks ago
- Intel's Analog Detailed Router☆39Updated 6 years ago