ganeshgore / spydrnet-physical

Related projects ⓘ

Alternatives and complementary repositories for spydrnet-physical

• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆21Updated last month
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆21Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 10 months ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆20Updated 8 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆21Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆23Updated last week
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆35Updated last week
• aolofsson / POSH
  ☆39Updated 4 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆31Updated 3 weeks ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated last month
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆16Updated 11 months ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 7 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆15Updated last week
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆35Updated 2 weeks ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆48Updated 10 months ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• aolofsson / IDEA
  ☆29Updated 4 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆45Updated 6 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 3 months ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 2 years ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆17Updated 3 weeks ago
• bogdanvuk / sydpy
  System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to Sys…
  ☆12Updated 8 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆47Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆21Updated last year