Alternatives and similar repositories for TritonCTS

Users that are interested in TritonCTS are comparing it to the libraries listed below

• aolofsson / POSH
  ☆44Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 5 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 5 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 7 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 5 years ago
• The-OpenROAD-Project-Attic / Resizer
  ☆15Updated 5 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated last week
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆49Updated 5 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆59Updated last year
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 4 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 5 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆56Updated 2 years ago