litex-hub / litespiLinks
Small footprint and configurable SPI core
☆46Updated last week
Alternatives and similar repositories for litespi
Users that are interested in litespi are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆66Updated last week
- FPGA USB stack written in LiteX☆132Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- ☆44Updated 10 months ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆58Updated 2 years ago
- Nitro USB FPGA core☆86Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated 2 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- LiteX development baseboards arround the SQRL Acorn.☆73Updated 10 months ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆43Updated 5 years ago
- Ultimate ECP5 development board☆115Updated 6 years ago
- Utilities for working with a Wishbone bus in an embedded device☆47Updated 4 months ago
- ☆45Updated 3 years ago
- FPGA board-level debugging and reverse-engineering tool☆39Updated 2 years ago
- VHDL library 4 FPGAs☆185Updated this week
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 3 years ago
- PicoRV☆43Updated 5 years ago
- ☆22Updated 3 years ago
- Project X-Ray Database: XC7 Series☆74Updated 4 years ago
- micropython ESP32 programmer/flasher for ECP5 JTAG☆74Updated 4 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated last month
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- assorted library of utility cores for amaranth HDL☆100Updated last year
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated this week
- ☆43Updated 5 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago