Alternatives and similar repositories for xfcp

Users that are interested in xfcp are comparing it to the libraries listed below

• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆63Updated 3 weeks ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated 2 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated this week
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 9 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆73Updated 2 weeks ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆117Updated last year
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated last week
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆107Updated last year
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 2 months ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 5 months ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆58Updated 2 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 6 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆81Updated 5 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆66Updated 8 years ago
• pulp-platform / axi_spi_slave
  ☆26Updated 4 years ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 7 months ago