Alternatives and similar repositories for xfcp

Users that are interested in xfcp are comparing it to the libraries listed below

• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆66Updated this week
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆47Updated 10 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆65Updated 4 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆67Updated 3 weeks ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆61Updated 2 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated last week
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 7 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• alexforencich / verilog-ft245
  Verilog FT245 to AXI stream interface
  ☆29Updated 7 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆67Updated 8 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆46Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆111Updated last year
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 6 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆115Updated 10 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago