alexforencich / xfcpLinks
Extensible FPGA control platform
☆62Updated 2 years ago
Alternatives and similar repositories for xfcp
Users that are interested in xfcp are comparing it to the libraries listed below
Sorting:
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- ☆32Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Small footprint and configurable JESD204B core☆42Updated last week
- ☆26Updated last year
- VHDL PCIe Transceiver☆28Updated 4 years ago
- UART models for cocotb☆29Updated 2 years ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆82Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- Various utilities for working with FPGAs☆13Updated 9 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆68Updated 8 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- ☆38Updated last year
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆60Updated this week
- USB Full Speed PHY☆44Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- ☆25Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago