alexforencich / xfcp
Extensible FPGA control platform
☆59Updated last year
Alternatives and similar repositories for xfcp:
Users that are interested in xfcp are comparing it to the libraries listed below
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- FPGA and Digital ASIC Build System☆74Updated last week
- ☆25Updated 3 years ago
- Small footprint and configurable JESD204B core☆42Updated 3 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- ☆26Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 7 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆54Updated 2 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 2 months ago
- ☆33Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆55Updated this week
- ☆69Updated last month
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- Wishbone interconnect utilities☆39Updated 2 months ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- Open FPGA Modules☆23Updated 6 months ago
- ☆59Updated 3 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 5 months ago
- Vivado build system☆68Updated 4 months ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- Verilog wishbone components☆114Updated last year