The-OpenROAD-Project / OpenDB
Database and Tool Framework for EDA
☆112Updated 4 years ago
Alternatives and similar repositories for OpenDB:
Users that are interested in OpenDB are comparing it to the libraries listed below
- UCSD Detailed Router☆85Updated 4 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆157Updated 4 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆133Updated 2 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆57Updated 11 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆102Updated last year
- IDEA project source files☆106Updated 5 months ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- A parallel global router using the Galois framework☆27Updated last year
- EDA physical synthesis optimization kit☆53Updated last year
- VLSI EDA Global Router☆72Updated 7 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆140Updated last week
- Delay Calculation ToolKit☆31Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆125Updated 9 months ago
- A LEF/DEF Utility.☆28Updated 5 years ago
- DATC RDF☆50Updated 4 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆133Updated 2 years ago
- ☆67Updated this week
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆119Updated 4 months ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- A Standalone Structural Verilog Parser☆91Updated 3 years ago
- RePlAce global placement tool☆232Updated 4 years ago
- ☆23Updated 4 years ago
- ☆105Updated 5 years ago
- A logic synthesis tool☆73Updated 3 weeks ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated this week
- Steiner Shallow-Light Tree for VLSI Routing☆51Updated 9 months ago
- ☆79Updated last month