The-OpenROAD-Project / OpenDB

Related projects ⓘ

Alternatives and complementary repositories for OpenDB

• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆121Updated last year
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆146Updated last year
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆79Updated 3 years ago
• pkuzjx / eda-collection
  ☆99Updated 4 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆55Updated 5 months ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆128Updated last year
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆122Updated 3 months ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆89Updated 4 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆97Updated 8 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆49Updated 11 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆97Updated 2 months ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆51Updated 2 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆46Updated 3 months ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆34Updated 4 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆53Updated 4 years ago
• ncsu-eda / FreePDK3
  ☆115Updated 3 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆26Updated 2 years ago
• IntelLabs / FloorSet
  ☆49Updated 2 weeks ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated last month
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆83Updated 2 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆75Updated last week
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago