The-OpenROAD-Project / OpenDBLinks
Database and Tool Framework for EDA
☆113Updated 4 years ago
Alternatives and similar repositories for OpenDB
Users that are interested in OpenDB are comparing it to the libraries listed below
Sorting:
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆55Updated 4 years ago
- UCSD Detailed Router☆87Updated 4 years ago
- IDEA project source files☆106Updated 6 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆168Updated 2 weeks ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- EDA physical synthesis optimization kit☆57Updated last year
- A parallel global router using the Galois framework☆29Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆104Updated last year
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆61Updated last year
- Delay Calculation ToolKit☆31Updated 2 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆145Updated last month
- DATC RDF☆50Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆136Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆126Updated 10 months ago
- VLSI EDA Global Router☆73Updated 7 years ago
- ☆24Updated 4 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆134Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- ☆105Updated 5 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆122Updated last week
- Steiner Shallow-Light Tree for VLSI Routing☆52Updated 10 months ago
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- ☆70Updated this week
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- GPU-based logic synthesis tool☆81Updated 10 months ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- A LEF/DEF Utility.☆30Updated 5 years ago