lnis-uofu / TIGFET-10nm-PDK
An open source PDK using TIGFET 10nm devices.
☆47Updated 2 years ago
Alternatives and similar repositories for TIGFET-10nm-PDK:
Users that are interested in TIGFET-10nm-PDK are comparing it to the libraries listed below
- A configurable SRAM generator☆42Updated last month
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆36Updated 2 years ago
- Open Source PHY v2☆25Updated 9 months ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆31Updated last month
- ☆40Updated 5 years ago
- Open source process design kit for 28nm open process☆48Updated 9 months ago
- Characterizer☆21Updated 5 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆39Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- Library of open source Process Design Kits (PDKs)☆33Updated this week
- Intel's Analog Detailed Router☆38Updated 5 years ago
- An automatic clock gating utility☆43Updated 7 months ago
- ☆20Updated 3 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆12Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- ☆16Updated 2 years ago
- ☆13Updated 7 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- ☆40Updated 2 years ago
- ☆33Updated 2 years ago
- sram/rram/mram.. compiler☆30Updated last year
- BAG framework☆40Updated 6 months ago
- repository for a bandgap voltage reference in SKY130 technology☆35Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 9 months ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆21Updated 6 years ago