Alternatives and similar repositories for containers:

Users that are interested in containers are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated 3 weeks ago
• pieter3d / simview
  ☆77Updated 11 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 11 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆65Updated 2 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆74Updated 3 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆144Updated last week
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆51Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆77Updated 2 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆73Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• efabless / caravel_user_project_analog
  ☆45Updated 2 weeks ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 7 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆40Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆145Updated last week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 7 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆136Updated last year
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆27Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆54Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆81Updated last week