hdl / containers
Building and deploying container images for open source electronic design automation (EDA)
☆109Updated 3 months ago
Alternatives and similar repositories for containers:
Users that are interested in containers are comparing it to the libraries listed below
- FuseSoC standard core library☆124Updated 3 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- FPGA tool performance profiling☆102Updated 10 months ago
- ☆76Updated 10 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- SystemVerilog frontend for Yosys☆68Updated last week
- 👾 Design ∪ Hardware☆72Updated 2 months ago
- ☆36Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- A curated list of awesome resources for HDL design and verification☆143Updated this week
- WAL enables programmable waveform analysis.☆142Updated 2 months ago
- A SystemVerilog source file pickler.☆53Updated 2 months ago
- Mutation Cover with Yosys (MCY)☆78Updated last month
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆64Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 4 months ago
- Announcements related to Verilator☆38Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆134Updated last year
- A command-line tool for displaying vcd waveforms.☆50Updated 11 months ago
- ☆31Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆42Updated 3 months ago
- ☆45Updated last month
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- Virtual development board for HDL design☆40Updated last year
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆72Updated 2 years ago
- FPGA and Digital ASIC Build System☆71Updated this week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆52Updated this week
- Naive Educational RISC V processor☆77Updated 3 months ago
- An automatic clock gating utility☆43Updated 6 months ago
- A complete open-source design-for-testing (DFT) Solution☆143Updated 2 months ago