hdl / containers
Building and deploying container images for open source electronic design automation (EDA)
☆107Updated last month
Related projects ⓘ
Alternatives and complementary repositories for containers
- FuseSoC standard core library☆115Updated last month
- Virtual development board for HDL design☆39Updated last year
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- FPGA tool performance profiling☆102Updated 8 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆62Updated last year
- A SystemVerilog source file pickler.☆51Updated last month
- Python script to transform a VCD file to wavedrom format☆74Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- ☆76Updated 8 months ago
- An abstract language model of VHDL written in Python.☆50Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- A JSON library implemented in VHDL.☆76Updated 2 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆53Updated 4 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆55Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Vivado build system☆71Updated this week
- An open-source HDL register code generator fast enough to run in real time.☆36Updated this week
- SystemVerilog synthesis tool☆169Updated this week
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆56Updated last week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆71Updated 2 years ago
- Naive Educational RISC V processor☆74Updated last month
- A curated list of awesome resources for HDL design and verification☆140Updated last week
- Streaming based VHDL parser.☆81Updated 4 months ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆45Updated last year
- ☆26Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆46Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆202Updated last week
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago