hdl / containersLinks
Building and deploying container images for open source electronic design automation (EDA)
☆115Updated last year
Alternatives and similar repositories for containers
Users that are interested in containers are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆150Updated this week
- ☆88Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Virtual development board for HDL design☆42Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆77Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- A command-line tool for displaying vcd waveforms.☆65Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Streaming based VHDL parser.☆84Updated last year
- A curated list of awesome resources for HDL design and verification☆164Updated last week
- Generate address space documentation HTML from compiled SystemRDL input☆58Updated 3 weeks ago
- Specification of the Wishbone SoC Interconnect Architecture☆50Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- Making cocotb testbenches that bit easier☆36Updated last month
- FPGA tool performance profiling☆103Updated last year
- Naive Educational RISC V processor☆92Updated 2 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆63Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- ☆34Updated 4 years ago
- A JSON library implemented in VHDL.☆80Updated 3 years ago
- SystemVerilog frontend for Yosys☆178Updated this week
- SpiceBind – spice inside HDL simulator☆56Updated 5 months ago
- Playing around with Formal Verification of Verilog and VHDL☆64Updated 4 years ago
- An abstract language model of VHDL written in Python.☆58Updated 3 weeks ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆70Updated 2 months ago
- SystemVerilog synthesis tool☆220Updated 9 months ago
- SystemVerilog Linter based on pyslang☆31Updated 7 months ago