SymbiFlow / vtr-verilog-to-routingLinks
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
☆38Updated last year
Alternatives and similar repositories for vtr-verilog-to-routing
Users that are interested in vtr-verilog-to-routing are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- ☆33Updated 2 years ago
- Framework Open EDA Gui☆73Updated 11 months ago
- ☆113Updated 4 years ago
- ☆38Updated 3 years ago
- Bitstream relocation and manipulation tool.☆49Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- ☆44Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 6 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆66Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- ☆63Updated 6 years ago
- Demo SoC for SiliconCompiler.☆62Updated 3 weeks ago
- Open Source PHY v2☆31Updated last year