SymbiFlow / vtr-verilog-to-routingLinks
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
☆38Updated last year
Alternatives and similar repositories for vtr-verilog-to-routing
Users that are interested in vtr-verilog-to-routing are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Framework Open EDA Gui☆74Updated last year
- Python interface to FPGA interchange format☆41Updated 3 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- ☆59Updated 3 years ago
- ☆33Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- ☆114Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆146Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆44Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- OpenFPGA☆34Updated 7 years ago
- An open-source custom cache generator.☆34Updated last year
- Open source EDA chip design flow☆51Updated 8 years ago
- FPGA tool performance profiling☆104Updated last year
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- ☆44Updated 5 years ago