SymbiFlow / vtr-verilog-to-routingLinks
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
☆38Updated last year
Alternatives and similar repositories for vtr-verilog-to-routing
Users that are interested in vtr-verilog-to-routing are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆90Updated 6 years ago
- ☆33Updated 3 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- ☆114Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Python interface to FPGA interchange format☆41Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- ☆44Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- FPGA tool performance profiling☆104Updated last year
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Framework Open EDA Gui☆74Updated last year
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- ☆59Updated 3 years ago
- ☆38Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago