The-OpenROAD-Project / alpha-release
Builds, flow and designs for the alpha release
☆54Updated 5 years ago
Alternatives and similar repositories for alpha-release:
Users that are interested in alpha-release are comparing it to the libraries listed below
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 4 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- BAG framework☆40Updated 8 months ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆57Updated 10 months ago
- ☆54Updated last year
- An automatic clock gating utility☆46Updated this week
- OpenPiton Design Benchmark☆25Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- A Standalone Structural Verilog Parser☆90Updated 3 years ago
- Qrouter detail router for digital ASIC designs☆57Updated last week
- ☆34Updated 5 years ago
- ☆35Updated 2 weeks ago
- ☆31Updated last year
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- IDEA project source files☆106Updated 5 months ago
- ☆103Updated 5 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Logic synthesis and ABC based optimization☆49Updated last week
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- ☆43Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated 2 years ago
- ☆36Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆57Updated 3 years ago
- ☆31Updated 3 months ago
- SystemVerilog frontend for Yosys☆88Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- Next generation CGRA generator☆111Updated this week
- ☆66Updated 2 years ago