SymbiFlow / yosysLinks
SymbiFlow WIP changes for Yosys Open SYnthesis Suite
☆39Updated last year
Alternatives and similar repositories for yosys
Users that are interested in yosys are comparing it to the libraries listed below
Sorting:
- Project X-Ray Database: XC7 Series☆71Updated 3 years ago
- CoreScore☆166Updated last week
- Small footprint and configurable embedded FPGA logic analyzer☆191Updated 2 weeks ago
- VHDL library 4 FPGAs☆181Updated 2 weeks ago
- nextpnr portable FPGA place and route tool☆20Updated last year
- PicoRV☆43Updated 5 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆44Updated 3 years ago
- FPGA USB stack written in LiteX☆129Updated 3 years ago
- An Open Source configuration of the Arty platform☆133Updated last year
- Ultimate ECP5 development board☆114Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆90Updated 11 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆122Updated 9 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- Documenting Lattice's 28nm FPGA parts☆144Updated last year
- VexRiscv-SMP integration test with LiteX.☆26Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated last month
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- A wishbone controlled scope for FPGA's☆84Updated last year
- A tiny POWER Open ISA soft processor written in Chisel☆111Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆150Updated 4 years ago
- Example litex Risc-V SOC and some example code projects in multiple languages.☆70Updated 2 years ago
- Board definitions for Amaranth HDL☆121Updated 2 months ago
- Virtual Development Board☆62Updated 3 years ago