SymbiFlow / yosys
SymbiFlow WIP changes for Yosys Open SYnthesis Suite
☆37Updated 10 months ago
Alternatives and similar repositories for yosys:
Users that are interested in yosys are comparing it to the libraries listed below
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆72Updated 2 years ago
- nextpnr portable FPGA place and route tool☆20Updated 4 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 2 weeks ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆86Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- FuseSoC standard core library☆124Updated 3 weeks ago
- CoreScore☆142Updated 4 months ago
- A utility for Composing FPGA designs from Peripherals☆170Updated 3 weeks ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 2 years ago
- ☆22Updated 2 years ago
- An Open Source configuration of the Arty platform☆124Updated last year
- System on Chip toolkit for Amaranth HDL☆85Updated 3 months ago
- Mutation Cover with Yosys (MCY)☆78Updated last month
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆78Updated 4 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆40Updated 9 months ago
- Documenting Lattice's 28nm FPGA parts☆142Updated last year
- ☆76Updated 10 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Extensible FPGA control platform☆55Updated last year
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Demo SoC for SiliconCompiler.☆56Updated this week
- Ultimate ECP5 development board☆103Updated 5 years ago
- VHDL library 4 FPGAs☆169Updated this week
- Xilinx Unisim Library in Verilog☆72Updated 4 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆52Updated last year
- A wishbone controlled scope for FPGA's☆74Updated last year