Alternatives and similar repositories for OpenSTA

Users that are interested in OpenSTA are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆550Updated this week
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆684Updated 3 weeks ago
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆385Updated 2 weeks ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆279Updated last month
• ALIGN-analoglayout / ALIGN-public
  ☆332Updated last week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆988Updated 3 months ago
• The-OpenROAD-Project / asap7
  ☆229Updated 10 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆496Updated this week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆303Updated 2 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆356Updated this week
• ncsu-eda / FreePDK3
  ☆186Updated 4 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆309Updated 3 months ago
• magical-eda / MAGICAL
  Machine Generated Analog IC Layout
  ☆264Updated last year
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆435Updated 4 months ago
• OSCC-Project / iEDA
  An open-source EDA infrastructure and tools from netlist to GDS
  ☆474Updated last week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆354Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆697Updated last month
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆200Updated 5 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆694Updated last month
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆605Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆475Updated 2 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,190Updated this week
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆595Updated 4 years ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆766Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆634Updated last week
• chipfoundry / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆328Updated last month
• IHP-GmbH / IHP-Open-PDK
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:
  ☆659Updated this week
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆372Updated 10 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆739Updated last week