The-OpenROAD-Project / OpenSTALinks
OpenSTA engine
☆480Updated this week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below
Sorting:
- A High-performance Timing Analysis Tool for VLSI Systems☆631Updated 2 years ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆447Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆335Updated this week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆214Updated 7 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- Magic VLSI Layout Tool☆543Updated this week
- SystemVerilog to Verilog conversion☆639Updated last month
- The UVM written in Python☆434Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆395Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆328Updated this week
- ☆303Updated 3 months ago
- An open-source static random access memory (SRAM) compiler.☆911Updated 2 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆329Updated 3 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆282Updated last week
- SystemRDL 2.0 language compiler front-end☆254Updated 3 months ago
- Build Customized FPGA Implementations for Vivado☆327Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆301Updated 3 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆282Updated last month
- EPFL logic synthesis benchmarks☆199Updated last month
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,112Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆298Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆581Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆557Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆457Updated last week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆721Updated last year
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆136Updated last year
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆178Updated 5 years ago
- ☆381Updated this week
- UVM 1.2 port to Python☆252Updated 4 months ago