OpenSTA engine
☆555Mar 17, 2026Updated this week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below
Sorting:
- A High-performance Timing Analysis Tool for VLSI Systems☆691Dec 26, 2025Updated 2 months ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,507Updated this week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,726Sep 15, 2025Updated 6 months ago
- Database and Tool Framework for EDA☆123Jan 25, 2021Updated 5 years ago
- ☆104Updated this week
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,132Mar 11, 2026Updated last week
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62May 28, 2024Updated last year
- Yosys Open SYnthesis Suite☆4,333Mar 14, 2026Updated last week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆590Mar 14, 2026Updated last week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,213Updated this week
- RePlAce global placement tool☆247Aug 13, 2020Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Nov 18, 2024Updated last year
- Deep learning toolkit-enabled VLSI placement☆956Feb 19, 2026Updated last month
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆130Feb 3, 2026Updated last month
- IO and Pin Placer for Floorplan-Placement Subflow☆23Aug 11, 2020Updated 5 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Aug 7, 2022Updated 3 years ago
- UCSD Detailed Router☆95Jan 5, 2021Updated 5 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆228Oct 26, 2024Updated last year
- An open-source static random access memory (SRAM) compiler.☆1,021Mar 12, 2026Updated last week
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,450Oct 28, 2024Updated last year
- A complete open-source design-for-testing (DFT) Solution☆182Aug 30, 2025Updated 6 months ago
- Magic VLSI Layout Tool☆621Updated this week
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆129Apr 23, 2023Updated 2 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- C++ logic network library☆281Sep 30, 2025Updated 5 months ago
- Builds, flow and designs for the alpha release☆54Dec 18, 2019Updated 6 years ago
- Logic synthesis and ABC based optimization☆54Mar 4, 2026Updated 2 weeks ago
- Showcase examples for EPFL logic synthesis libraries☆203Apr 5, 2024Updated last year
- ☆15Oct 24, 2019Updated 6 years ago
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- An Open-source FPGA IP Generator☆1,058Mar 13, 2026Updated last week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆402Mar 5, 2026Updated 2 weeks ago
- IDEA project source files☆112Oct 15, 2025Updated 5 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆194May 19, 2025Updated 10 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated 3 weeks ago
- Rsyn – An Extensible Physical Synthesis Framework☆137Jul 20, 2024Updated last year
- ☆114Feb 2, 2021Updated 5 years ago