The-OpenROAD-Project / OpenSTALinks
OpenSTA engine
☆508Updated last week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below
Sorting:
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆495Updated this week
- A High-performance Timing Analysis Tool for VLSI Systems☆658Updated 3 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆360Updated last week
- ☆318Updated 3 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆268Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 11 months ago
- ☆194Updated 6 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆292Updated 3 months ago
- Machine Generated Analog IC Layout☆255Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆416Updated last month
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆187Updated 5 years ago
- An open-source static random access memory (SRAM) compiler.☆952Updated 3 months ago
- SystemVerilog to Verilog conversion☆668Updated 3 months ago
- Magic VLSI Layout Tool☆568Updated last week
- RePlAce global placement tool☆239Updated 5 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆344Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,147Updated this week
- ☆176Updated 4 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆294Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆611Updated last week
- Build Customized FPGA Implementations for Vivado☆343Updated this week
- ☆149Updated 2 years ago
- The UVM written in Python☆458Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆751Updated last year
- lowRISC Style Guides☆460Updated 3 months ago
- EPFL logic synthesis benchmarks☆213Updated last week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆617Updated last week
- Common SystemVerilog components☆661Updated 2 weeks ago
- An abstraction library for interfacing EDA tools☆714Updated 2 weeks ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆313Updated 7 months ago