OpenSTA engine
☆574Apr 23, 2026Updated last week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A High-performance Timing Analysis Tool for VLSI Systems☆694Dec 26, 2025Updated 4 months ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,623Updated this week
- Database and Tool Framework for EDA☆125Jan 25, 2021Updated 5 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,769Mar 25, 2026Updated last month
- ☆110Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,160Updated this week
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Apr 8, 2026Updated 3 weeks ago
- Yosys Open SYnthesis Suite☆4,416Updated this week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆617Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,222Updated this week
- RePlAce global placement tool☆251Aug 13, 2020Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Nov 18, 2024Updated last year
- Deep learning toolkit-enabled VLSI placement☆979Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- IO and Pin Placer for Floorplan-Placement Subflow☆24Aug 11, 2020Updated 5 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆132Apr 4, 2026Updated 3 weeks ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆60Aug 7, 2022Updated 3 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆229Oct 26, 2024Updated last year
- UCSD Detailed Router☆98Jan 5, 2021Updated 5 years ago
- An open-source static random access memory (SRAM) compiler.☆1,048Apr 17, 2026Updated last week
- An abstraction library for interfacing EDA tools☆762Updated this week
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,494Oct 28, 2024Updated last year
- Magic VLSI Layout Tool☆641Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A complete open-source design-for-testing (DFT) Solution☆186Aug 30, 2025Updated 8 months ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆130Apr 23, 2023Updated 3 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Builds, flow and designs for the alpha release☆54Dec 18, 2019Updated 6 years ago
- C++ logic network library☆289Sep 30, 2025Updated 7 months ago
- Logic synthesis and ABC based optimization☆55Apr 9, 2026Updated 3 weeks ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆418Apr 22, 2026Updated last week
- Showcase examples for EPFL logic synthesis libraries☆205Apr 5, 2024Updated 2 years ago
- ☆15Oct 24, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- An Open-source FPGA IP Generator☆1,087Updated this week
- SystemVerilog to Verilog conversion☆725Mar 28, 2026Updated last month
- IDEA project source files☆112Apr 15, 2026Updated 2 weeks ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆196May 19, 2025Updated 11 months ago
- Rsyn – An Extensible Physical Synthesis Framework☆139Jul 20, 2024Updated last year
- ☆114Feb 2, 2021Updated 5 years ago