The-OpenROAD-Project / OpenSTALinks
OpenSTA engine
☆528Updated last week
Alternatives and similar repositories for OpenSTA
Users that are interested in OpenSTA are comparing it to the libraries listed below
Sorting:
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆530Updated this week
- A High-performance Timing Analysis Tool for VLSI Systems☆677Updated 5 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆378Updated this week
- ☆324Updated this week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆301Updated last month
- The UVM written in Python☆486Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆430Updated 3 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆221Updated last year
- ☆216Updated 8 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆350Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- SystemVerilog to Verilog conversion☆680Updated 2 weeks ago
- Build Customized FPGA Implementations for Vivado☆347Updated this week
- An open-source static random access memory (SRAM) compiler.☆967Updated last month
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆192Updated 5 years ago
- Machine Generated Analog IC Layout☆260Updated last year
- RePlAce global placement tool☆242Updated 5 years ago
- ☆183Updated 4 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆623Updated 3 weeks ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,174Updated this week
- EPFL logic synthesis benchmarks☆220Updated 3 weeks ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆757Updated last year
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆641Updated this week
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆162Updated 7 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆366Updated 9 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆321Updated last week
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆187Updated 6 months ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year