Alternatives and similar repositories for yosys-f4pga-plugins

Users that are interested in yosys-f4pga-plugins are comparing it to the libraries listed below

• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 9 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆121Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated 2 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 9 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆65Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆49Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated this week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago
• efabless / mpw_precheck
  ☆44Updated 10 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated 3 weeks ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆146Updated 2 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 10 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆130Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆187Updated this week
• pieter3d / simview
  ☆88Updated 3 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆43Updated 2 months ago
• efabless / caravel_user_project_analog
  ☆51Updated 11 months ago