Alternatives and similar repositories for firrtl-spec

Users that are interested in firrtl-spec are comparing it to the libraries listed below

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆186Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 7 months ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆27Updated 2 years ago
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆57Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆80Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 10 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated last month
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆117Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆178Updated 3 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆131Updated 4 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆136Updated last week
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆91Updated last week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆80Updated last year
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆96Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆184Updated 9 months ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆255Updated 4 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆201Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 4 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆109Updated 5 months ago